Datasheet

3.0 Parallel Interface (Continued)
14
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USBN9603/USBN9604
3.1.1 Standard Access Mode
The standard access sequence for non-multiplexed mode is to write the address to the ADDR register and then read or write
the data from/to the DATA_OUT/DATA_IN register. The DATA_OUT register is updated after writing to the ADDR register.
The ADDR register or the DATA_OUT/DATA_IN register is selected with the A0 input.
3.1.2 Burst Mode
In burst mode, the ADDR register is written once with the desired memory address of any of the on-chip registers. Then
consecutive reads/writes are performed to the DATA_IN/DATA_OUT register without previously writing a new address. The
content of the DATA_OUT register for read operations is updated once after every read or write.
3.1.3 User Registers
The following table gives an overview of the parallel interface registers in non-multiplexed mode.
The reserved bits return undefined data on read and should be written with 0.
Address Register (ADDR)
The ADDR register acts as a pointer to the internal memory. This register is write only and is cleared on reset.
Data Output Register (DATA_OUT)
The DATA_OUT register is updated with the contents of the memory register to which the ADDR register is pointing. Update
occurs under the following conditions:
1. After the ADDR register is written.
2. After a read from the DATA_OUT register.
3. After a write to the DATA_IN register.
This register is read only and holds undefined data after reset.
Data Input Register (DATA_IN)
The DATA_IN register holds the data written to the device address to which ADDR points. This register is write only and is
cleared on reset.
A0 Access bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
0 Read DATA_OUT
0 Write DATA_IN
1 Read Reserved
1 Write Reserved ADDR5-0
Obsolete