Datasheet
UCD9248
18
17
16
14
15
13
12
11
3
2
4
10
9
8
7
5
1
6
43
44
45
47
46
48
49
50
58
59
57
51
52
53
54
56
60
55
38
37
36
34
35
33
32
31
23
22
24
30
29
28
27
25
21
26
63
64
65
67
66
68
69
70
78
79
77
71
72
73
74
76
80
75
19
20
42
41
39
40
62
61
ADCref
CS-4A
CS-3A
CS-2A
Vin/Iin
Vtrack
Temperature
V33DIO
DGND1
SEQ-3
SRE-1B
SRE-1A
nRESET
TRCK
FLT-1A
FLT-1B
FLT-2A
FLT-2B
PMBus_Clk
PMBus_Data
DPWM-1A
DPWM-1B
DPWM-2A
DPWM-2B
DPWM-3A
DPWM-3B
DPWM-4A
DPWM-4B
FLT-3A
Sync-Out
Sync-In
SEQ-1
SRE-4A
DGND2
PMBus_Alert
PMBus_Control
SRE-2B
SRE-3A
TMUX-0
TMUX-1
FLT-3B
FLT-4A
FLT-4B
TCK
TDO
TDI
TMS
nTRST
PGood
SRE-4B
SRE-2A
SRE-3B
SEQ-2
TMUX-2
DGND3
V33DIO
V33D
V33A
BPCap
AGND1
AGND2
EAp1
EAn1
EAp2
EAn2
EAp3
EAn3
EAn4
EAp4
V33FB
Aux-in (AD13)
Aux-in (AD14)
CS-4B
CS-3B
CS-1A
ADDR-1
ADDR-0
CS-2B
CS-1B
AGND3
UCD9248
SLVSA33A –JANUARY 2010–REVISED AUGUST 2012
www.ti.com
The UCD9248 is available in an 80-pin TQFP package (PFC).
Figure 3. Pin Assignment Diagram
TYPICAL APPLICATION SCHEMATIC
Figure 4 shows the UCD9248 power supply controller as part of a system that provides the regulation of one
eight-phase power supply. The loop for the power supply is created by the voltage output feeding into the
differential voltage error ADC (EADC) input, and completed by DPWM outputs feeding into the gate drivers for
each power stage.
The ±V
sense
rail signal must be routed to the EAp/EAn input that matches the number of the lowest DPWM
configured as part of the rail. (See more detail in Flexible Rail/Power Stage Configuration.)
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