Datasheet

rail-rail spread

t =

Clk

reset

PWMgatedrive

output

SysClk

SyncIn

EADCtrigger

SyncOut

DPWMEngine(1of4)

Switchperiod

Currentbalanceadj

Compensatoroutput

(Calculateddutycycle)

EADCtrigger

threshold

highres

ramp

counter

UCD9248

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SLVSA33A –JANUARY 2010–REVISED AUGUST 2012

Figure 11. DPWM Engine

Flexible Rail/Power Stage Configuration

The UCD9248 can control up to four rails, each of which can comprise a programmable number of power stages.

Constraints on the mapping of power stages to rails are described in detail in the UCD92xx PMBus Command

Reference under the PHASE_INFO command.

While there is significant flexibility in terms of mapping power stages to output rails, the differential voltage

feedback signals (EAP/EAN) cannot be re-mapped through any commands, and therefore, must be connected to

the proper input on the circuit board. Because the EADC sample trigger for a given front end stage is derived

from the ramp timer of the first (lowest numbered) DPWM on the rail, the system must ensure that the number of

the EADC and the number of the first DPWM match. For example, consider a two rail configuration in which 4

power stages (1A, 2A, 1B and 2B) are assigned to the first rail and 2 power stages (3A and 4A) to the second.

The first DPWM on the first rail is 1; its voltage feedback must be through EAP1/EAN1. The first DPWM on the

second rail is 3; its voltage feedback must be through EAP3/EAN3. (In this configuration EAP2/EAN2 and

EAP4/EAN4 are unused and are disabled to reduce unnecessary power consumption.)

DPWM Phase Distribution

The number of voltage rails is configured using the PHASE_INFO PMBus command. The UCD9248

automatically synchronizes the first power stage of each voltage rail. The phase (in time) of each 1st power stage

is shifted by an amount in order to minimize input current ripple. The amount that each 1st power stage is shifted

is:

(6)

Where t

is the period of the rail with the fastest switching frequency.

The ratio 3/13 is chosen because it is close to 1/4, but it is a prime ratio. This should ensure that any

configuration of rails and power stages should not have the leading edge of the DPWM signal aligned.