Datasheet

UCD9248

SLVSA33A –JANUARY 2010–REVISED AUGUST 2012

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Figure 10. Digital Compensation

The nonlinear gain block allows a different gain to be applied to the system when the error voltage deviates from

zero. Typically Limit 0 and Limit 1 would be configured with negative values between –1 and –32 and Limit 2 and

Limit 3 would be configured with positive values between 1 and 31. However, the gain thresholds do not have to

be symmetric. For example, the four limit registers could all be set to positive values causing the Gain 0 value to

set the gain for all negative errors and a nonlinear gain profile would be applied to only positive error voltages.

The cascaded 1st order filter section is used to generate the third zero and third pole.

DPWM Engine

The output of the compensator feeds the high resolution DPWM engine. The DPWM engine produces the pulse

width modulated gate drive output from the device. In operation, the compensator calculates the necessary duty

cycle as a digital number representing a value from 0 to 100%. This duty cycle value is multiplied by the

configured period to generate a comparator threshold value. This threshold is compared against the high speed

switching period counter to generate the desired DPWM pulse width. This is shown in Figure 11.

Each DPWM engine can be synchronized to another DPWM engine or to an external sync signal via the

SYNC_IN and SYNC_OUT pins. Configuration of the synchronization function is done through a MFR_SPECIFIC

PMBus command. See the DPWM Synchronization section for more details.