Datasheet

p
2
R
R =
1 K-
P
1
R
R =
K
+Vout
-Vout
R1
R2
EAP
EAN
C2
Rin
Ioff
UCD9248
SLVSA33A –JANUARY 2010–REVISED AUGUST 2012 www.ti.com
Table 3. Analog Front End Resolution (continued)
AFE_GAIN for EFFECTIVE ADC RESOLUTION DIGITAL ERROR VOLTAGE
AFE GAIN
PMBus COMMAND (mV) DYNAMIC RANGE (mV)
1 2 4 –128 to 124
2 4 2 –64 to 62
3 8 1 –32 to 31
The AFE variable gain is one of the compensation coefficients that are stored when the device is configured by
issuing the CLA_GAINS PMBus command. Compensator coefficients are arranged in several banks: one bank
for start/stop ramp or tracking, one bank for normal regulation mode and one bank for light load mode. This
allows the user to trade-off resolution and dynamic range for each operational mode.
The EADC, which samples the error voltage, has high accuracy, high resolution, and a fast conversion time.
However, its range is limited as shown in Table 3. If the output voltage is different from the reference by more
than this, the EADC reports a saturated value at –32 LSBs or 31 LSBs. The UCD9248 overcomes this limitation
by adjusting the Vref DAC up or down in order to bring the error voltage out of saturation. In this way, the
effective range of the ADC is extended. When the EADC saturates, the Vref DAC is slewed at a rate of 0.156
V/ms, referred to the EA differential inputs.
The differential feedback error voltage is defined as V
EA
= V
EAP
– V
EAN
. An attenuator network using resistors R1
and R2 (see Figure 9) should be used to ensure that V
EA
does not exceed the maximum value of V
ref
when
operating at the commanded voltage level. The commanded voltage level is determined by the PMBus settings
described in the Output Voltage Adjustment section.
Figure 9. Input Offset Equivalent Circuit
Voltage Sense Filtering
Conditioning should be provided on the EAP and EAN signals. Figure 9 a divider network between the output
voltage and the voltage sense input to the controller. The resistor divider is used to bring the output voltage
within the dynamic range of the controller. When no attenuation is needed, R2 can be left open and the signal
conditioned by the low-pass filter formed by R1 and C2.
As with any power supply system, maximize the accuracy of the output voltage by sensing the voltage directly
across an output capacitor as close to the load as possible. Route the positive and negative differential sense
signals as a balanced pair of traces or as a twisted pair cable back to the controller. Put the divider network close
to the controller. This ensures that there is low impedance driving the differential voltage sense signal from the
voltage rail output back to the controller. The resistance of the divider network is a trade-off between power loss
and minimizing interference susceptibility. A parallel resistance (R
P
) of 1kΩ to 4kΩ is a good compromise. Once
R
P
is chosen, R
1
and R
2
can be determined from the following formulas.
(1)
(2)
16 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated