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UCD9246

www.ti.com

SLVSA34 –JANUARY 2010

Digital PWM System Controller

FEATURES

Tool to Simulate, Configure, and Monitor

Power Supply Performance

• Fully Configurable Multi-Output and Multi-

Phase Non-Isolated DC/DC PWM Controller

APPLICATIONS

• Controls Up to 4 Voltage Rails and Up to 6

• Industrial/ATE

Phases

• Networking Equipment

• Supports Switching Frequencies Up to 2MHz

• Telecommunications Equipment

with 250 ps Duty-Cycle Resolution

• Servers

• Up To 1mV Closed Loop Resolution

• Storage Systems

• Hardware-Accelerated, 3-Pole/3-Zero

• FPGA, DSP and Memory Power

Compensator with Non-Linear Gain for

Improved Transient Performance

DESCRIPTION

• Supports Multiple Soft-Start and Soft-Stop

The UCD9246 is a multi-rail, multi-phase

Configurations Including Prebias Start-up

synchronous buck digital PWM controller designed for

• Supports Voltage Tracking, Margining and

non-isolated DC/DC power applications. This device

Sequencing

integrates dedicated circuitry for DC/DC loop

• Supports Current and Temperature Balancing

management with flash memory and a serial interface

for Multi-Phase Power Stages

to support configurability, monitoring and

management.

• Supports Phase Adding/Shedding for

Multi-Phase Power Stages

The UCD9246 was designed to provide a wide

variety of desirable features for non-isolated DC/DC

• Sync In/Out Pins Align DPWM Clocks Between

converter applications while minimizing the total

Multiple UCD92xx Devices

system component count by reducing external

• 12-Bit Digital Monitoring of Power Supply

circuits. The solution integrates multi-loop

Parameters Including:

management with sequencing, margining, tracking

– Input/Output Current and Voltage

and intelligent phase management to optimize for

total system efficiency. Additionally, loop

– Temperature at Each Power Stage

compensation and calibration are supported without

• Multiple Levels of Over-current Fault

the need to add external components.

Protection:

To facilitate configuring the device, the Texas

– External Current Fault Inputs

Instruments Fusion Digital Power™ Designer is

– Fast Overcurrent Protection

provided. This PC based Graphical User Interface

– Current Continually Digitally Monitored

offers an intuitive interface to the device. This tool

allows the design engineer to configure the system

• Over- and Under-voltage Fault Protection

operating parameters for the application, store the

• Over-temperature Fault Protection

configuration to on-chip non-volatile memory and

• Enhanced Nonvolatile Memory with Error

observe both frequency domain and time domain

Correction Code (ECC)

simulations for each of the power stage outputs.

• Device Operates From a Single Supply with an

TI has also developed multiple complementary power

Internal Regulator Controller That Allows

stage solutions – from discrete drivers in the UCD7k

Operation Over a Wide Supply Voltage Range

family to fully tested power train modules in the PTD

family. These solutions have been developed to

• Supported by Fusion Digital Power™

complement the UCD9k family of system power

Designer, a Full Featured PC Based Design

controllers.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Fusion Digital Power, Auto-ID are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (36 pages)

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UCD9246 www.ti.
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UCD9246 SLVSA34 – JANUARY 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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UCD9246 www.ti.com SLVSA34 – JANUARY 2010 ELECTRICAL CHARACTERISTICS (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ERROR AMPLIFIER INPUTS EAPn, EANn VCM Common mode voltage each pin VERROR Internal error voltage range AFE_GAIN field of CLA_GAINS = 0 (1) –0.15 1.848 –256 248 mV EAP-EAN Error voltage digital resolution AFE_GAIN field of CLA_GAINS = 3 REA Input Impedance Ground reference 0.5 IOFFSET Input offset current 1 kΩ source impedence –5 V 3 MΩ 5 µA 1 1.
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UCD9246 SLVSA34 – JANUARY 2010 www.ti.com ADC MONITORING INTERVALS AND RESPONSE TIMES The ADC operates in a continuous conversion sequence that measures each rail's output voltage, each power stage's output current, plus four other variables (external temperature, Internal temperature, input voltage and current, and tracking input voltage). The length of the sequence is determined by the number of output rails (NumRails) and total output power stages (NumPhases) configured for use.
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UCD9246 www.ti.com SLVSA34 – JANUARY 2010 HARDWARE FAULT DETECTION LATENCY The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer. PARAMETER tFAULT tCLF TEST CONDITIONS MAX UNIT 15 + 3 × NumPhases µs Time to disable DPWM output based on corresponding active FLTpin High level on FAULT pin Time to disable the first DPWM output based on internal analog comparator fault Step change in CS voltage from 0V to 2.
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UCD9246 SLVSA34 – JANUARY 2010 www.ti.com Figure 1.
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UCD9246 www.ti.
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UCD9246 SLVSA34 – JANUARY 2010 www.ti.com AGND3 CS-1B CS-2B ADDR-0 ADDR-1 CS-1A V33FB EAN4 EAP4 EAN3 EAP3 EAN2 EAP2 EAN1 EAP1 AGND2 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 The UCD9246 is available in an 64-pin QFN package (RGC).
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UCD9246 www.ti.com SLVSA34 – JANUARY 2010 UCD7231 Power Stage Vin Vin Vin +3.
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UCD9246 SLVSA34 – JANUARY 2010 www.ti.com PIN DESCRIPTIONS PIN NO. 10 PIN NAME DESCRIPTION 1 CS-4A Power stage 4A current sense input and input to analog comparator 4 2 CS-3A Power stage 3A current sense input and input to analog comparator 3 3 CS-2A Power stage 2A current sense input and input to analog comparator 2 4 Vin/Iin Input supply sense, alternates between Vin and Iin 5 Vtrack Voltage track input 6 Temperature Temperature sense input 7 V33DIO Digital I/O 3.
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UCD9246 www.ti.com PIN NO. SLVSA34 – JANUARY 2010 PIN NAME DESCRIPTION 47 BPCap 1.8V bypass capacitor connection 48 AGND1 Analog Ground 49 AGND2 Analog Ground 50 EAP1 Error analog, differential voltage. Positive channel #1 input 51 EAN1 Error analog, differential voltage. Negative channel #1 input 52 EAP2 Error analog, differential voltage. Positive channel #2 input 53 EAN2 Error analog, differential voltage. Negative channel #2 input 54 EAP3 Error analog, differential voltage.
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UCD9246 SLVSA34 – JANUARY 2010 www.ti.com FUNCTIONAL OVERVIEW The UCD9246 contains four fusion power peripherals (FPP). Each FPP can be configured to regulated up to four DC/DC converter outputs. There are six PWM outputs that can be assigned to drive the converter outputs. Each FPP consists of: • A differential input error voltage amplifier • A 10-bit DAC used to set the output regulation reference voltage. • A fast ADC with programmable input gain to digitally measure the error voltage.
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UCD9246 www.ti.com SLVSA34 – JANUARY 2010 Table 1. PMBus Address Bins (continued) PMBus ADDRESS RPMBus PMBus RESISTANCE (kΩ) 6 100 5 86.6 4 75 3 64.9 2 56.2 1 48.7 0 42.2 short – A low impedance (short) on either address pin that produces a voltage below the minimum voltage causes the PMBus address to default to address 126. A high impedance (open) on either address pin that produces a voltage above the maximum voltage also causes the PMBus address to default to address 126.
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UCD9246 SLVSA34 – JANUARY 2010 www.ti.com Some circuits in the device require 1.8V that is generated internally from the 3.3V supply. This voltage requires a 0.1 µF to 1 µF bypass capacitor from BPCap to ground. To Power Stage Vin FCX491A +3.3 V 10 kW 4.7 mF 0.1 mF +1.8 V V33A V33D BPCap V33FB 0.1 mF UC9246 Figure 6. 3.3V Shunt Regulator Controller I/O Power On Reset The UCD9246 has an integrated power-on reset (POR) circuit that monitors the supply voltage.
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UCD9246 www.ti.com SLVSA34 – JANUARY 2010 OPERATION Command VOUT_MAX VOUT_MARGIN_HIGH + 3:1 Mux VOUT_COMMAND VOUT_ SCALE_ LOOP Limiter Vref DAC VOUT_MARGIN_LOW VOUT_CAL_OFFSET Figure 7. PMBus Voltage Adjustment Methods For a complete description of the commands supported by the UCD9246 see the UCD92xx PMBUS Command Reference. Each of these commands can also be issued from the Texas Instruments Fusion Digital Power™ Designer program.
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UCD9246 SLVSA34 – JANUARY 2010 www.ti.com Table 3. Analog Front End Resolution AFE_GAIN for PMBus COMMAND AFE GAIN EFFECTIVE EADC RESOLUTION (mV) DIGITAL ERROR VOLTAGE DYNAMIC RANGE (mV) 0 1 8 –256 to 248 1 2 4 –128 to 124 2 4 2 –64 to 62 3 8 1 –32 to 31 The AFE variable gain is one of the compensation coefficients that are stored when the device is configured by issuing the CLA_GAINS PMBus command.
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UCD9246 www.ti.com SLVSA34 – JANUARY 2010 Where K= VEA VOUT @ VOUT_SCALE_LOOP (3) It is recommended that a capacitor be placed across the lower resistor of the divider network. This acts as an additional pole in the compensation and as an anti-alias filter for the EADC. To be effective as an anti-alias filter, the corner frequency should be 35% to 40% of the switching frequency. Then the capacitor is calculated as: 1 C2 = 2 p ´ 0.
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UCD9246 SLVSA34 – JANUARY 2010 www.ti.com Figure 10. Digital Compensation The nonlinear gain block allows a different gain to be applied to the system when the error voltage deviates from zero. Typically Limit 0 and Limit 1 would be configured with negative values between –1 and –32 and Limit 2 and Limit 3 would be configured with positive values between 1 and 31. However, the gain thresholds do not have to be symmetric.
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UCD9246 www.ti.com SLVSA34 – JANUARY 2010 DPWM Engine (1 of 4) SysClk SyncIn Clk high res ramp counter reset S Switch period R PWM gate drive output Current balance adj Compensator output EADC trigger (Calculated duty cycle) EADC trigger SyncOut threshold Figure 11. DPWM Engine Flexible Rail/Power Stage Configuration The UCD9246 can control up to four rails, each of which can comprise a programmable number of power stages.
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UCD9246 SLVSA34 – JANUARY 2010 www.ti.com The PHASE_INFO PMBus command is also used to configure the number of power stages driving each voltage rail. When multiple power stages are configured to drive a voltage rail, the UCD9246 automatically distributes the phase of each DPWM output to minimize ripple.
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UCD9246 www.ti.com SLVSA34 – JANUARY 2010 Table 4. Output Current Filter Time Constants NUMBER OF OUTPUT RAILS OUTPUT CURRENT SAMPLING INTERVALS (µs) FILTER TIME CONSTANTS (ms) 1 200 0.7 2 400 1.4 3 600 2.1 4 800 2.8 This averaged current measurement is used for output current fault detection; see “Over-Current Detection” section. In response to a PMBus request for a current reading, the device returns an average current value.
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UCD9246 SLVSA34 – JANUARY 2010 www.ti.com stage has the highest measured current and which stage has the lowest measured current. To balance the currents while maintaining a constant total current, the adjustment value for the power stage with the lowest current is increased by the same amount as the adjustment value for the power stage with the highest current is decreased.
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UCD9246 www.ti.com SLVSA34 – JANUARY 2010 Input Voltage and Current Monitoring The Vin/Iin pin on the UCD9246 monitors the input voltage and current. To measure both input voltage and input current, an external multiplexer is required, see Figure 4. If measurement of only the input voltage, and not input current, is desired, then a multiplexer is not needed. The multiplexer is switched between voltage and current using the TMUX-0 signal.
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UCD9246 SLVSA34 – JANUARY 2010 www.ti.com +3.3 V Vcc Temperature Temp _1A Temp _1B A0 Temp _2A Temp _2B A2 A3 Temp _3A A7 Temp _4A A5 S2 TMUX-2 A6 S1 TMUX-1 A7 S0 TMUX-0 A A1 CD74HC4051 Vee Gnd E Figure 12. Temperature Mux (1 rail, 8 phases) Below is an example of a system with two output voltage rails driven by 3 power stages each. The first output voltage rail is driven with DPWM-1A, DPWM-1B and DPWM-3A. The second output voltage rail is driven with DPWM-2A, DPWM-2B and DPWM-4A.
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UCD9246 www.ti.com SLVSA34 – JANUARY 2010 Table 5. Temperature Sensor Mapping TEMPERATURE MUX INPUT POWER STAGE A0 DPWM-1A A1 DPWM-1B A2 DPWM-3A A3 DPWM-2A A4 DPWM-2B A5 DPWM-4A A6 n/c A7 n/c Temperature Balancing Temperature balancing between phases is performed by adjusting the current such that cooler phases draw a larger share of the current.
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UCD9246 SLVSA34 – JANUARY 2010 www.ti.com When a voltage rail is in its idle state, the DPWM and SRE outputs are disabled, and the differential voltage on the EAP/EAN pins are monitored by the controller. During idle the Vref DAC is adjusted to minimize the error voltage. If there is a pre-bias (that is, a non-zero voltage on the regulated output), then the device can begin the start ramp from that voltage with a minimum of disturbance.
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UCD9246 www.ti.com SLVSA34 – JANUARY 2010 Method 1: Each rail has programmable delay times, TON_DELAY and TOFF_DELAY, before beginning a soft start ramp or a soft stop ramp, and programmable ramp times, TON_RISE and TOFF_FALL determine how long the ramp takes. These PMBus commands are defined in the UCD92xx PMBUS Command Reference. The parameters can also be configured using the Fusion Digital Power™ Designer GUI (see http://focus.ti.com/docs/toolsw/folders/print/fusion_digital_power_designer.html).
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UCD9246 SLVSA34 – JANUARY 2010 www.ti.com Each rail can be optionally configured to monitor a sequencing input pin for a specified period of time after it turns on and reaches its power good threshold. If the programmable timeout is reached before the input pin state matches its defined logic level, the rail is shut down, and a status error posted. This feature could be used, for example, to ensure that an LDO on the board did turn on when the main system voltage came up.
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UCD9246 www.ti.com SLVSA34 – JANUARY 2010 Note that since the compensator and DPWM are digital, their transfer functions are known exactly and can be divided out of the measured open-loop gain. In this way the UCD9246 can accurately measure the power stage/load plant transfer function in situ (in place), on the factory floor or in an end equipment application and send the measurement data back to a host through the PMBus interface without the need for external test equipment.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCD9246RGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 UCD9246RGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 UCD9246RGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCD9246RGCR VQFN RGC 64 2000 367.0 367.0 38.0 UCD9246RGCR VQFN RGC 64 2000 367.0 367.0 38.0 UCD9246RGCT VQFN RGC 64 250 210.0 185.0 35.0 UCD9246RGCT VQFN RGC 64 250 210.0 185.0 35.
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