Datasheet

UCD9244
SLVSAL6A –NOVEMBER 2010– REVISED FEBRUARY 2011 www.ti.com
HARDWARE FAULT DETECTION LATENCY
The controller contains hardware fault detection circuits that are independent of the ADC monitoring sequencer.
PARAMETER TEST CONDITIONS MAX TIME UNIT
Time to disable DPWM output base on active FAULT pin
t
FAULT
High level on FAULT pin 18 µs
signal
Time to disable the DPWM A output based on internal Switch
t
CLF
Step change in CS voltage from 0V to 2.5V 4
analog comparator Cycles
PMBUS/SMBUS/I
2
C
The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and
PMBus are shown below.
Figure 1. I
2
C/SMBus/PMBus Timing in Extended Mode Diagram
I
2
C/SMBus/PMBus TIMING REQUIREMENTS
T
A
= –40°C to 125°C, 3V < V
33
< 3.6V, typical values at T
A
= 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
f
SMB
SMBus/PMBus operating frequency Slave mode; SMBC 50% duty cycle 10 1000 kHz
f
I2C
I C operating frequency Slave mode; SCL 50% duty cycle 10 1000 kHz
t
(BUF)
Bus free time between start and stop 4.7 µs
t
(HD:STA)
Hold time after (repeated) start 0.26 µs
t
(SU:STA)
Repeated start setup time 0.26 µs
t
(SU:STO)
Stop setup time 0.26 µs
t
(HD:DAT)
Data hold time Receive mode 0 ns
t
(SU:DAT)
Data setup time 50 ns
t
(TIMEOUT)
Error signal/detect See
(1)
35 ms
t
(LOW)
Clock low period 0.5 µs
t
(HIGH)
Clock high period See
(2)
0.26 50 µs
t
(LOW:SEXT)
Cumulative clock low slave extend time See
(3)
25 ms
t
FALL
Clock/data fall time Rise time t
RISE
= V
ILMAX
– 0.15) to (V
IHMIN
+ 0.15) 1000 ns
t
RISE
Clock/data rise time Fall time t
FALL
= 0.9 V
33
to (V
ILMAX
– 0.15) 1000 ns
(1) The UCD9244 times out when any clock low exceeds
t(TIMEOUT)
.
(2) t
(HIGH)
, max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction involving UCD9244 that is
in progress.
(3) t
(LOW:SEXT)
is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
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