Datasheet

SW sync
1 0.95
EADC_SAMPLE_TRIGGER 248ns
F F
³ - +
UCD9244
SLVSAL6A –NOVEMBER 2010– REVISED FEBRUARY 2011 www.ti.com
DPWM Phase Synchronization
DPWM synchronization provides a method to link the timing between voltage rails controlled by the UCD92xx
device--either internally or between devices. The configuration of the synchronization between rails is performed
by the issuing the SYNC_CONFIG command. For details of issuing this command, see the UCD92xx PMBUS
Command Reference (SLUU337). The synchronization behavior can also be configured using the Fusion Digital
Power Designer software. Below is a summary of the function.
Each digital pulse width modulator (PWM) engine in the UCD92xx controller can accept a sync signal that resets
the PWM ramp generator. The ramp generator can be set to free-run, accept a reset signal from another internal
PWM engine, or accept a reset signal from the external SyncIn pin. In this way the PWM timers can be
"daisy-chained" to set up the desired phase relationship between power stages.
The PWM engine reset input can accept the following inputs
Table 6. Sync Trigger Inputs
None (free run)
DPWM 1
DPWM 2
DPWM 3
DPWM 4
SyncIn Pin
Table 7. Available Source For SyncOut
Disabled
DPWM 1
DPWM 2
DPWM 3
DPWM 4
When configuring a PWM engine to run synchronous to another internal PWM output, set the switching
frequency of each PWM output to the same value using the FREQUENCY_SWITCH PMBus command. Set the
time point where the controller samples the voltage to be regulated by setting the EADC_SAMPLE_TRIGGER
value to the minimum value (228-240 nsec before the end of the switching period).
When configuring a PWM engine to run synchronous to an external sync signal, the switching period must be set
to be longer than the period of the sync signal by setting the value of the FREQUENCY_SWITCH command to
be lower than the frequency of the sync signal. This way the external sync signal will reset the PWM ramp
counter before it is internally reset. In this operating condition, the error ADC sample trigger time must be set to:
(6)
where F
sw
is the switching frequency set by FREQUENCY_SWITCH and F
sync
is the minimum synchronization
frequency. The factor of 0.95 is due to the 5% tolerance on the internal clock in the controller. This will ensure
that the regulation voltage is sampled "just in time" to calculate the appropriate control effort for each switching
period. This is shown in Figure 15.
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