Datasheet

high res
ramp
counter
Clk
reset
PWM gate drive output
SysClk
SyncIn
EADC trigger
SyncOut (not available
on UCD9244)
S
R
DPWM Engine (1 of 4)
Switch period
Current balance adj
Compensator output
(Calculated duty cycle)
EADC trigger
threshold
UCD9244
www.ti.com SLVSAL6A –NOVEMBER 2010–REVISED FEBRUARY 2011
DPWM Engine
The output of the compensator feeds the high resolution DPWM engine. The DPWM engine produces the pulse
width modulated gate drive output from the device. In operation, the compensator calculates the necessary duty
cycle as a digital number representing a percentage from 0 to 100%. The duty cycle value is multiplied by the
configured period to generate a comparator threshold value. This threshold is compared against the high speed
switching period counter to generate the desired DPWM pulse width. This is shown in Figure 14.
Each DPWM engine can be synchronized to another DPWM engine or to an external sync signal via the SyncIn
and SyncOut pins. Configuration of the synchronization function is done through a MFR_SPECIFIC PMBus
command. See the DPWM Synchronization section for more details.
Figure 14. DPWM Engine
Rail/Power Stage Configuration
Unlike many other products in the UCD92xx family, the UCD9244 does not support assigning power stages to
arbitrary rails, or combining multiple power stages on the same rail. The UCD9244 supports up to two
single-phase rails, and the channel number of each rail’s DPWM output must match that of its EAP/EAN
feedback inputs.
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