Datasheet

( )
2
2
Z Z Z
DC
P2
S s
1
Q
H s K
s
s 1
+ +
w w
=
æ ö
+
ç ÷
w
è ø
UCD9244
SLVSAL6A –NOVEMBER 2010– REVISED FEBRUARY 2011 www.ti.com
Figure 13. Digital Compensator
To calculate the values of the digital compensation filter continuous-time design parameters K
DC
, F
Z
ands Q
Z
are
entered into the Fusion Digital Power Designer software (or it calculates them automatically). Where the
compensating filter transfer function is
(5)
There are approximate limits the design parameters K
DC
, F
Z
ands Q
Z
. Though design parameters beyond these
upper a lower bounds can be used to calculate the discrete-time filter coefficients, there will be significant
round-off error when the continuous-time floating-point design parameters are converted to the discrete-time
fixed-point integer coefficients to be downloaded to the controller.
APPROXIMATE
DESIGN PARAMETER UNITS
LOWER BOUND UPPER BOUND
K
DC
60 103 dB
F
Z
3 kHz Fsw/5 kHz
Q
Z
0.1 5.0 n/a
The nonlinear gain block allows a different gain to be applied to the system when the error voltage deviates from
zero. Typically Limit 0 and Limit 1 would be configured with negative values between –1 and –32 and Limit 2 and
Limit 3 would be configured with positive values between 1 and 31. However, the gain thresholds do not have to
be symmetrical. For example, the four limit registers could all be set to positive values causing the Gain 0 value
to set the gain for all negative errors and a nonlinear gain profile would be applied to only positive error voltages.
The cascaded 1
st
order filter section is used to generate the third zero and third pole.
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