Datasheet

V33FB
0.1μ
R1
Vin
4.7μ
0.1μ
FCX491A
UCD9244
To Power Stage
+3.3V
+1.8V
V33A
V33D
BPCap
0.
1μ
( )
in be
1
E
SINK
V 3.3 V
R
I
I
1
- -
=
+
b +
UCD9244
SLVSAL6A –NOVEMBER 2010– REVISED FEBRUARY 2011 www.ti.com
Bias Supply Generator (Shunt Regulator Controller)
The I/O and analog circuits in the UCD9244 require 3.3V to operate. This can be provided using a stand-alone
external 3.3V supply, or it can be generated from the main input supply using an internal shunt regulator and an
external transistor. Regardless of which method is used to generate the 3.3V supply, bypass capacitors of 0.1 µF
and 4.7 µF should be connected from V33A and V33D to ground near the device. An additional bypass capacitor
from 0.1 to 1 µF must be connected from the BPCap pin to ground for the internal 1.8V supply to the device’s
logic circuits.
Figure 9 shows a typical application using the external transistor. The base of the transistor is driven by a resistor
R1 to Vin and a transconductance amplifier whose output is on the V33FB pin. The NPN emitter becomes the
3.3V supply for the chip.
Figure 9. 3.3V Shunt Regulator Controller I/O
In order to generate the correct voltage on the base of the external pass transistor, the internal transconductance
amplifier sinks current into the V33FB pin and a voltage is produced across R1. This resistor value should be
chosen so that ISINK is in the range from 0.2 to 0.4mA. R1 is defined as
(1)
Where I
SINK
is the current into the V33FB pin; V
in
is the power supply input voltage, typically 12V; I
E
is the current
draw of the device and any pull up resistors tied to the 3.3V supply; and β is the beta of the pass transistor. For
I
SINK
= 0.3 mA, V
in
=12V, β=99, V
be
= 0.7V and I
E
=50mA, this formula selects R1 = 10kΩ. Weaker transistors or
larger current loads will require less resistance to maintain the desired I
SINK
current. For example, lowering β to
40 would require R1 = 5.23 kΩ; likewise, an input voltage of 5V requires a value of 1.24 kΩ for R1.
Power-On Reset
The UCD9244 has an integrated power-on reset (POR) circuit that monitors the supply voltage. At power-up, the
POR circuit detects the V33D rise. When V33D is greater than V
RESET
, the device initiates an internal startup
sequence. At the end of the startup sequence, the device begins normal operation, as defined by the
downloaded device PMBus configuration.
External Reset
The device can be forced into the reset state by an external circuit connected to the nRESET pin. A logic low
voltage on this pin holds the device in reset. To avoid an erroneous trigger caused by noise, a 10kΩ pull up
resistor to 3.3V is recommended.
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Product Folder Link(s) :UCD9244