Datasheet

Lower Half
VID_A = bit 0
VID_B = bit 1
VID_C = bit 2
VID_S
VID_A
VID_B
VID_C
UpperHalf
VID_A = bit 3
VID_B = bit 4
VID_C = bit 5
Lower Half
VID_A = bit 0
VID_B = bit 1
VID_C = bit 2
Upper Half
VID_A = bit 3
VID_B = bit 4
VID_C = bit 5
VOUT
VID_S
TfTr
ThdTsu Tchi
Tclo
VID_A,
VID_B,
VID_C
VOUT
Tvo
UCD9244
www.ti.com SLVSAL6A –NOVEMBER 2010–REVISED FEBRUARY 2011
The falling edge of the VID_S line triggers the UCD9244 to read bits 2:0 on the three VID data lines. The rising
edge of VID_S triggers the UCD9244 to read bits 5:3 on the three VID data lines and calculate a new VOUT
setpoint. This calculation takes from 35 to 135µs. The output voltage will then slew to the new setpoint voltage at
the rate specified by the VOUT_TRANSITION_RATE PMBus command.
Figure 6. 6-Bit VID Data Transfer
The set-up time on the data lines is 0 µs. All four VID lines must hold at the same level for some time after a
change in the VID_S line to allow the UCD9244 to read and validate the data signals and perform necessary
voltage calculations. The UCD9244 can tolerate single hold times as short as 70µs, but does not have sufficient
computation power to sustain continuous VID messaging that quickly. It is expected that the hold time will be at
least 125µs for sustained operations. It is recommended that the DSP only send VID messages when the
regulated voltage needs to change; sending the same VID code repeatedly and continuously provides no benefit.
Figure 7 and Table 3 illustrate the critical timing measurements as they apply to the 6-bit VID interface.
Figure 7. 6-bit VID Timing
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