Datasheet

UCD9244

SLVSAL6A –NOVEMBER 2010– REVISED FEBRUARY 2011

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Regardless of which VID mode is used, the commanded output voltage reference is set according to this formula:

Vref_cmd = (VID_CODE × VID_Slope) + VID_Offset,

where

VID_Slope = (VID_Vout_High – VID_Vout_Low) / ((2^VID_Format) -1),

and

VID_Offset = VID_Vout_Low.

The VID_Vout_High, VID_Vout_Low, and VID_Format values are set using the VID_CONFIG PMBus command.

The same command is used to set the initial VID code that will be used at power-up. In addition, the

VID_CONFIG command also sets the initial voltage that the device ramps to at the end of the soft start; and

defines a lockout interval over which the VID is ignored during the soft start.

VID Lockout Interval: Because the VID signals may be originating from a device that is being powered by the

UCD9244, the voltage levels on the VID signal may not be valid logic levels until the supply voltage at the

powered device has stabilized. For this reason a configurable lockout interval is applied each time the regulated

output voltage is turned on. The lockout interval timer starts when the output voltage reaches the top of the

soft-start ramp. Positive values range from 1 to 32767 ms, with 1 ms resolution. A value of 0 will enable the VID

inputs immediately at the top of the start ramp. Negative values disable the lockout, allowing the VID inputs to

remain active all the time regardless of the output voltage state. The default value is 0.

4-Bit VID Mode: In 4-bit VID mode, the four VID input signals are used to provide the four bits of VID data, as

shown in the table below. The VID lines are level-sensitive, and are periodically polled every 400µs. When the

VID lines are changed to command a new voltage, there may be a delay of 500 to 600µs while the UCD9244

confirms that the VID signal levels are stable. The output voltage will then slew to the new setpoint voltage at the

rate specified by the PMBus VOUT_TRANSITION_RATE command.

PIN PURPOSE RAIL 1 RAIL 2 RAIL 3 RAIL 4

VID_A Data bit 0 (least significant bit) VID1A VID2A VID3A VID4A

VID_B Data bit 1 VID1B VID2B VID3B VID4B

VID_C Data bit 2 VID1C VID2C VID3C VID4C

VID_S Data bit 3 (most significant bit) VID1S VID2S VID3S VID4S

6-Bit VID Mode: In 6-bit VID mode, the four VID input signals are used to provide the six bits of VID data, as

shown in the table below. Each of the three data lines (VID_A, VID_B, and VID_C) carries two bits of data per

VID code. The bits are clocked and selected by the VID_S select line.

PIN PURPOSE RAIL 1 RAIL 2 RAIL 3 RAIL 4

VID_A Data bit 0 when VID_S is low, VID1A VID2A VID3A VID4A

Data bit 3 when VID_S is high

VID_B Data bit 1 when VID_S is low, VID1B VID2B VID3B VID4B

Data bit 4 when VID_S is high

VID_C Data bit 2 when VID_S is low, VID1C VID2C VID3C VID4C

Data bit 5 when VID_S is high

VID_S Select Line: VID1S VID2S VID3S VID4S

Low= LSB, High = MSB

Product Folder Link(s) :UCD9244