Datasheet

Vref DAC
CPU
V
EA
V
EAP
V
ead
PMBus
V
EAN
Vref = 1.563 mV/LSB
G
AFE
= 1, 2, 4, or 8
G
eADC
= 8mV/LSB
6-bit
result
EADC
UCD9222
www.ti.com SLVSAL7A –NOVEMBER 2010–REVISED FEBRUARY 2011
For a complete description of the commands supported by the UCD9222 see the UCD92xx PMBUS Command
Reference (SLUU337). Each of these commands can also be issued from the Texas Instruments Fusion Digital
Power™ Designer program. This Graphical User Interface (GUI) PC program issues the appropriate commands
to configure the UCD9222 device.
Calibration
To optimize the operation of the UCD9222, PMBus commands are supplied to enable fine calibration of output
voltage, output current, and temperature measurements. The supported commands and related calibration
formulas may be found in the UCD92xx PMBUS Command Reference (SLUU337).
Analog Front End (AFE)
Figure 11. Analog Front End Block Diagram
The UCD9222 senses the power supply output voltage differentially through the EAP and EAN pins. The error
amplifier utilizes a switched capacitor topology that provides a wide common mode range for the output voltage
sense signals. The fully differential nature of the error amplifier also ensures low offset performance.
The output voltage is sampled at a programmable time (set by the EADC_SAMPLE_TRIGGER PMBus
command). When the differential input voltage is sampled, the voltage is captured in internal capacitors and then
transferred to the error amplifier where the value is subtracted from the set-point reference which is generated by
the 10-bit Vref DAC as shown in Figure 11. The resulting error voltage is then amplified by a programmable gain
circuit before the error voltage is converted to a digital value by the error ADC (EADC). This programmable gain
is configured through the PMBus and affects the dynamic range and resolution of the sensed error voltage as
shown in Table 5. The internal reference gains and offsets are factory-trimmed at the 4x gain setting, so it is
recommended that this setting be used whenever possible.
Table 5. Analog Front End Resolution
AFE_GAIN for EFFECTIVE ADC DIGITAL ERROR VOLTAGE
AFE Gain
PMBus Command RESOLUTION (mV) DYNAMIC RANGE (mV)
0 1x 8 –256 to 248
1 2x 4 –128 to 124
2 (Recommended) 4x 2 –64 to 62
3 8x 1 –32 to 31
The AFE variable gain is one of the compensation coefficients that are stored when the device is configured by
issuing the CLA_GAINS PMBus command. Compensator coefficients are arranged in several banks: one bank
for start/stop ramp or tracking, one bank for normal regulation mode and one bank for light load mode. This
allows the user to trade-off resolution and dynamic range for each operational mode.
The EADC, which samples the error voltage, has high accuracy, high resolution, and a fast conversion time.
However, its range is limited as shown in Table 5. If the output voltage is different from the reference by more
than this, the EADC repoºrts a saturated value at –32 LSBs or 31 LSBs. The UCD9222 overcomes this limitation
by adjusting the Vref DAC up or down in order to bring the error voltage out of saturation. In this way, the
effective range of the ADC is extended. When the EADC saturates, the Vref DAC is slewed at a rate of 0.156
V/ms, referred to the EA differential inputs.
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