Datasheet

UCD9081
SLVS813B –JUNE 2008–REVISED DECEMBER 2010 www.ti.com
CONSIDERATIONS FOR MONX INPUT SERIES RESISTANCE, R
S
R
S
is the series impedance between the sampled voltage source (low impedance power supply output) and the
UCD9081 MONx input pin. This resistance can affect UCD9081 sampling accuracy if it is too large. In most
cases (when the power supply being monitored has a lower VOUT than the UCD9081 voltage reference being
used) this resistance is low and can be ignored. In cases where a voltage divider is used to scale the monitored
voltage below the voltage reference, the impedance of this network must be chosen so that it does not adversely
affect the analog to digital converter (ADC) conversion accuracy. The equivalent series impedance (R
S
) of the
divider network is just the parallel combination of the pullup and pulldown resistors.
The UCD9081 has an internal clock (DCO) whose frequency is set by ROSC on pin 32. The DCO frequency can
be affected by several factors including supply voltage and temperature. This clock is used by the ADC to set up
an ADC sample or gate time (T
GATE
) at each MONx pin. The voltage sampled must be allowed to settle
sufficiently during T
GATE
. The settling time is affected by the UCD9081 internal capacitance and R
S
. To allow for
sufficient settling time over DCO frequency, supply voltage, and temperature variation, choose R
S
< 6kΩ.
ESTIMATING UCD9081 REPORTING ACCURACY OVER VARIATIONS IN ADC VOLTAGE
REFERENCE
The UCD9081 uses a 10 bit ADC. The ADC in the UCD9081 derives its reference voltage (V
R+
) from either the
external (V
CC
pin) or internal (V
REF+
) reference voltage to scale the digitally reported voltage. The least significant
bit (LSB) voltage value is V
LSB
= V
R+
/2
n
where n = 10 and V
R+
is the reference voltage used (either external
V
CC
= 3.3V nominal, or internal V
REF+
= 2.5V nominal). For external V
R+
= V
CC
= 3.3V, V
LSB
= 3.3/1024 = 3.22mV
and for internal V
R+
= V
REF+
= 2.5V, V
LSB
= 2.5/1024 = 2.44mV.
The error in the reported voltage is a function of the ADC linearity error(s) as well as variations in the ADC
reference voltage. The total unadjusted error (E
TUE
) for the ADC in the UCD9081 is ±5 LSB and the variation of
the internal 2.5V reference is ±6% maximum. V
TUE
is calculated as V
LSB
× E
TUE
for the particular reference
voltage used. The reported voltage error will be the sum of the reference voltage error and the ADC total
unadjusted error. At lower monitored voltages, E
TUE
may dominate reported error while at higher monitored
voltages V
R+
will dominate the reported error. Reported error (percent) can be calculated using the equation
below where REFTOL is V
R+
tolerance, V
ACT
is actual voltage monitored (at the UCD9081 MONx pin), and V
R+
is
the nominal voltage of the ADC reference.
RPT
ERR
= [(1 + REFTOL]/V
ACT
] × [V
R+
× E
TUE
/1024 + V
ACT
] - 1
Shown below are four examples using the equation above to estimate reported error:
V
R+
= 2.5V, REFTOL = 6%, V
ACT
= 0.25V, RPT
ERR
= 11.2%
V
R+
= 2.5V, REFTOL = 6%, V
ACT
= 2.25V, RPT
ERR
= 6.6%
V
R+
= 3.3V, REFTOL = 1%, V
ACT
= 0.25V, RPT
ERR
= 7.5%
V
R+
= 3.3V, REFTOL = 1%, V
ACT
= 2.25V, RPT
ERR
= 1.7%
In addition to the reporting errors due to ADC and voltage reference, there can be additional errors due to divider
resistor tolerance when monitoring voltages higher than V
R+
. These errors can be added to the reporting error
described above.
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