Datasheet

UCD9081

SLVS813B –JUNE 2008–REVISED DECEMBER 2010

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USER DATA

User data (128 bytes) can be stored in the UCD9081 FLASH memory at location 0x1080 to 0x10FF. Writes to

the User Data section of memory are performed as follows:

1. Unlock flash memory by writing the value 0x02 to the FLASHLOCK register

2. Write the address of the USER DATA section of memory (WADDR = 0x1080)

3. Write the constant 0xBADC to update memory (WDATA = 0xBADC)

4. Write the address of the USER DATA section of memory again (WADDR = 0x1080)

5. Write the data (WDATA = <varies>). Repeat steps 4 and 5 as necessary depending on the data segment

size used. Increment the address as necessary.

6. Lock flash memory after the last byte of the last segment is written by writing the value 0x00 to the

FLASHLOCK register

To read the User Data section of memory, follow the procedure for reading memory outlined in the section on

WADDR and WDATA .

C ADDRESS SELECTION

The UCD9081 supports 7-bit I

C addressing. The UCD9081 selects an I

C address by sampling the logic level of

the four digital inputs to the device (ADDR1–ADDR4) during the RESET interval. When the UCD9081 is released

from RESET, the ADDRx logic levels are latched and the I

C address is assigned as shown in Figure 8 .

A7 = 1 A6 = 1 A5 = 0 A4 = ADDR4/GPO4 A3 = ADDR3/GPO3 A2 = ADDR2/GPO2 A1 = EN8/ADDR1/GPO1

Figure 8. I

C ADDRESS = 0x60–0x6F

External pullup/pulldown resistors are required to configure the I

C address; the UCD9081 does not have internal

bias resistors. Note that the 7-bit I

C address refers to the address bits only, not the read/write bit in the first byte

of the I

C protocol. The base I

C address is 0x60 and the I

C general call address (0x00) is not supported.

After the initialization process of the UCD9081 is complete, these four pins can be used for general-purpose

outputs.

C TRANSACTIONS

The UCD9081 can be configured and monitored via I

C memory-mapped registers. Registers that are

configurable (can be written) via an I

C write operation are implemented using an I

C unidirectional data transfer,

from the master to slave, with a stop bit between transactions.

Product Folder Link(s) :UCD9081