Datasheet

Minor
7
6 5 4 3 2 1 0
r r r r r r r r
Major
1415 13 12 11 10 9 8 7 6 5 4 3 2 1 0
rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0
RAIL8
rc-0 rc-0 rc-0 rc-0 rc-0 rc-0 rc-0rc-0
RAIL7 RAIL6 RAIL5 RAIL4 RAIL3 RAIL2 RAIL1
RAILnMeaning
0NoalarmpendingforR n
1 AlarmpendingforRAILn
AIL
FLASHLOCK
7 6 5 4 3 2 1 0
rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0
FLASHLOCK
0x00 Lockflash(default)
0x01 Flashisbeingupdated
0x02 Unlockflash(beforeconfiguration)
UCD9081
SLVS813B –JUNE 2008–REVISED DECEMBER 2010 www.ti.com
VERSION
The VERSION register provides the user with access to the device revision of the UCD9081. The format of this
register is a nibble-based major.minor format as shown below.
RAILSTATUS
The RAILSTATUS1 and RAILSTATUS2 registers are two 8-bit read-only registers that provide a bit mask to
represent the error status of the rails as indicated in the following diagram.
Bits 15:8 are RAILSTATUS1 and bits 7:0 are RAILSTATUS2. These are read as two 8-bit registers or as a single
16-bit register.
If a bit is set in these registers, then the ERROR register is read to further ascertain the specific error. Bits in the
RAILSTATUS1 and RAILSTATUS2 registers are cleared when read.
FLASHLOCK
The FLASHLOCK register is used to lock and unlock the configuration memory on the UCD9081 when updating
the configuration. The Configuring the UDC9081 section details this process.
The format for the FLASHLOCK register is as follows:
RESTART
The RESTART register provides the capability for the I
2
C host to force a RESET or Shutdown of the UCD9081.
This is an 8-bit register, and when a value of 0x00 is written to the register, the UCD9081 RESET occurs and the
rails are re-sequenced. Note that in order to respond to this I
2
C request properly, there is a 50-ms delay before
the system is restarted, so that the I
2
C ACK can take place.
When a value of 0xC0 is written to the register, all rails and GPOs are shutdown according to the time delays
specified in the system shutdown configuration. Once this procedure is complete, the UCD9081 will continue
monitoring.
18 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s) :UCD9081