Datasheet

IICError
RAIL Error
NVERRLOG PARAMError
FWError
RegisterStatus
0
12
3
4
56
7
rc-0rc-0 rc-0
r r
r-0
IICError
0
1
NoI CPHY layererror
2
2
I CPHY layererror
RAIL Error
NVERRLOG
FWError
PARAMError
0
1
0
1
0
1
0
1
NoRAIL errorpending
RAIL errorpending
ERRORpointstorun-timeerrorlog
ERRORpointstonon-volatilelog(ifheldinRESET)
andentriespresentinnon-volatilelog
NoError(normaloperation)
Devicefirmwareerrordetected,deviceisidle
NoError(normaloperation)
Parametersinvalid,lastconfigloaded
Register
Status
00
01
10
11
Meaning
Noerror
Invalidaddress
Readaccesserror
Writeaccesserror
r
Meaning
Meaning
Meaning
Meaning
Meaning
UCD9081
www.ti.com SLVS813B –JUNE 2008–REVISED DECEMBER 2010
STATUS
STATUS is an 8-bit read-only register. This register provides real-time status information about the state of the
UCD9081. The following bits are defined.
Reading of the STATUS register clears the register except for the NVERRLOG bit, which is maintained until the
device is reset. Descriptions of the different errors are below.
The IICERROR bit is set when an I
2
C access fails. This is most often a case where the user has accessed an
invalid address or performed an illegal number of operations for a given register (for example, reading 3 bytes
from a 2-byte register). In the event of an I
2
C error when the IICERROR is set, bits 1:0 of the STATUS register
further define the nature of the error as shown in the preceding figure.
The RAIL error bit is set to alert the user to an issue with one of the voltage rails. When this bit is set, the user is
advised to query the RAILSTATUS register to further ascertain which RAIL input(s) have an issue. The user may
then query the ERROR registers to get further information about the nature of the error condition.
The NVERRLOG bit is set to 1 upon device RESET if the UCD9081 contains entries in the FLASH error log.
Note that this bit is the only bit that is not automatically cleared by a read of the STATUS register; this bit is only
cleared during UCD9081 RESET (if the nonvolatile error log is empty).
The FW Error bit is set to 1 if the device firmware memory contents are corrupted.
The PARAM Error bit is set to 1 if the contents of the UCD9081 configuration memory are invalid. If this occurs,
the UCD9081 will load the last known good configuration to ensure device reliability.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s) :UCD9081