Datasheet

UCD9081
www.ti.com SLVS813B –JUNE 2008–REVISED DECEMBER 2010
MONITORING THE UCD9081
Register Map
The UCD9081 allows all monitoring of the system through the I
2
C interface on the device. The following is the
memory map of the supported registers in the system. The detail of each of these registers is given in the next
section as well.
Note that the UCD9081 supports functionality to increment the I
2
C register address value automatically when a
register is being accessed in order to more efficiently access blocks of like registers. The following table also
shows the amount that the register address is incremented for each register access.
REGISTER NAME ADDRESS ACCESS ADJUSTMENT AFTER ACCESS
RAIL1H 0x00 r +1 (0x01)
RAIL1L 0x01 r +1 (0x02)
RAIL2H 0x02 r +1 (0x03)
RAIL2L 0x03 r +1 (0x04)
RAIL3H 0x04 r +1 (0x05)
RAIL3L 0x05 r +1 (0x06)
RAIL4H 0x06 r +1 (0x07)
RAIL4L 0x07 r +1 (0x08)
RAIL5H 0x08 r +1 (0x09)
RAIL5L 0x09 r +1 (0x0A)
RAIL6H 0x0A r +1 (0x0B)
RAIL6L 0x0B r +1 (0x0C)
RAIL7H 0x0C r +1 (0x0D)
RAIL7L 0x0D r +1 (0x0E)
RAIL8H 0x0E r +1 (0x0F)
RAIL8L 0x0F r –15 (0x00)
ERROR1 0x20 r +1 (0x21)
ERROR2 0x21 r +1 (0x22)
ERROR3 0x22 r +1 (0x23)
ERROR4 0x23 r +1 (0x24)
ERROR5 0x24 r +1 (0x25)
ERROR6 0x25 r –5 (0x20)
STATUS 0x26 r 0 (0x26)
VERSION 0x27 r 0 (0x27)
RAILSTATUS1 0x28 r +1 (0x29)
RAILSTATUS2 0x29 r –1 (0x28)
FLASHLOCK 0x2E rw 0 (0x2E)
RESTART 0x2F w 0 (0x2F)
WADDR1 0x30 rw +1 (0x31)
WADDR2 0x31 rw –1 (0x30)
WDATA1 0x32 rw +1 (0x33)
WDATA2 0x33 rw –1 (0x32)
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