Datasheet

UCD9081
SLVS813B –JUNE 2008–REVISED DECEMBER 2010 www.ti.com
DEVICE RESET
UCD9081 RESET occurs due to one of the following conditions:
• External RST pin is asserted
• Power is applied to the device (power-on-reset) or power is cycled
• A sequence event occurs as a result of a configured rail alarm event
• RESTART command is issued over the I
2
C bus
During RESET, the following takes place:
• All ENx and GPOx pins are placed in a high-impedance state
• All internal timers are reset to zero
• The I
2
C address pins (ADDR1-ADDR4) are sampled and the device address is assigned accordingly
• All ENx and GPOx pins are driven to their inactive levels
• The UCD9081 runs a checksum function to validate its memory contents
• If there are no errors, the device starts sequencing according to the current sequencer configuration
During this time, the UCD9081 will not respond to host requests made over the I
2
C bus.
In order to ensure the integrity of data within the device, the device runs a checksum function during RESET. If
the configuration parameters of the device are valid, the UCD9081 will begin operating according to the current
sequencer configuration. If the configuration parameters are invalid, the UCD9081 will overwrite the current
configuration parameters with the last known good configuration and the device will begin operating with these
parameters. This can cause a delay in the RESET time. Note that in order to establish a copy of the valid
configuration, UCD9081 RESET time will be delayed the first time a new configuration is loaded.
VOLTAGE REFERENCE
The analog to digital converter in the UCD9081 has a selectable voltage reference, V
R+
. The voltage reference
can either be an internally generated 2.5V reference or an external reference derived from V
CC
. The external
reference is recommended for those systems requiring more accurate voltage readings. See the Estimating
UCD9081 Reporting Accuracy Over Variations In ADC Voltage Reference section for information on calculating
the accuracy of each reference.
VOLTAGE MONITORING
The UCD9081 can monitor eight voltage rails through the MONx terminals of the device (MON1–MON8). The
UCD9081 samples these eight input channels and uses the selected reference to convert the voltages to digital
values. These values are accessible via the I
2
C interface. When monitoring a voltage rail that has a nominal
voltage larger than the selected reference, a resistor divider network is typically used. The design must ensure
that the source impedance of the resistor network is chosen properly in order to maintain the accuracy of the
analog to digital conversion. For more details, see the Application Information section.
The UCD9081 allows the user to independently specify the following for each monitored rail:
• overvoltage threshold (OV)
• undervoltage threshold (UV)
• out of regulation time or glitch width (OORW)
• maximum time for regulation (MTFR)
The MTFR is used to determine whether or not a rail starts successfully after being enabled.
The UCD9081 also has the ability to ignore glitches. Glitches are fault conditions that last less than the specified
OORW for that rail. Ignoring glitches may be useful in the case where the power supply is known to be noisy but
still operates well. Ignoring glitches does not affect the monitoring capability of the UCD9081 with respect to
detecting sustained UV or OV faults. It simply prevents the UCD9081 from logging glitch faults to the error log.
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