Datasheet

Start
Stop
Clk
ACK
Clk
ACK
PMB_Clk
PMB_Data
T
LOW:SEXT
T
LOW:MEXT
T
LOW:MEXT
T
LOW:MEXT
UCD90124A
www.ti.com SLVSAN8 –JANUARY 2012
PMBus/SMBus/I
2
C
The timing characteristics and timing diagram for the communications interface that supports I
2
C, SMBus and
PMBus is shown below.
I
2
C/SMBus/PMBus TIMING REQUIREMENTS
T
A
= –40°C to 85°C, 3 V < V
DD
< 3.6 V; typical values at T
A
= 25°C and V
CC
= 2.5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FSMB SMBus/PMBus operating frequency Slave mode, SMBC 50% duty cycle 10 400 kHz
FI2C I
2
C operating frequency Slave mode, SCL 50% duty cycle 10 400 kHz
t
(BUF)
Bus free time between start and stop 4.7 μs
t
(HD:STA)
Hold time after (repeated) start 0.26 μs
t
(SU:STA)
Repeated-start setup time 0.26 μs
t
(SU:STO)
Stop setup time 0.26 μs
t
(HD:DAT)
Data hold time Receive mode 0 ns
t
(SU:DAT)
Data setup time 50 ns
t
(TIMEOUT)
Error signal/detect See
(1)
35 ms
t
(LOW)
Clock low period 0.5 μs
t
(HIGH)
Clock high period See
(2)
0.26 50 μs
t
(LOW:SEXT)
Cumulative clock low slave extend time See
(3)
25 ms
t
f
Clock/data fall time See
(4)
120 ns
t
r
Clock/data rise time See
(5)
120 ns
(1) The device times out when any clock low exceeds t
(TIMEOUT)
.
(2) t
(HIGH)
, Max, is the minimum bus idle time. SMBC = SMBD = 1 for t > 50 ms causes reset of any transaction that is in progress. This
specification is valid when the NC_SMB control bit remains in the default cleared state (CLK[0] = 0).
(3) t
(LOW:SEXT)
is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop.
(4) Fall time t
f
= 0.9 VDD to (V
IL
MAX – 0.15)
(5) Rise time t
r
= (V
IL
MAX – 0.15) to (V
IH
MIN + 0.15)
Figure 1. I
2
C/SMBus Timing Diagram
Figure 2. Bus Timing in Extended Mode
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