Datasheet

Vmarg
Closed Loop
Margining
UCD90124A
VMON1
GPIO1
12V
V33FB
V33A
V33D
GPIO2
5V OUT
VMON2
3.3V OUT
VMON3
2.5V OUT
VMON4
1.8V OUT
3.3V_UCD
1.5V OUT
1.2V OUT
0.8V OUT
I0.8V
TEMP0.8V
VMON5
VMON6
VMON7
VMON8
VMON9
VMON10
I12V
TEMP12V VMON12
VMON11
INA196
I12V
12V OUT
5V OUT
/EN
DC-DC 1
VOUT
VFB
VIN
3.3V OUT
/EN
DC-DC 2
VOUT
VFB
VIN
GPIO3
2.5V OUT
/EN
DC-DC 3
VOUT
VFB
VIN
GPIO4
12V OUT
/EN
LDO1
VOUT
VIN
1.8V OUT
GPIO5
GPIO6
GPIO7
GPIO8
/EN
LDO2
VOUT
VIN
1.5V OUT
/EN
LDO3
VOUT
VIN
1.2V OUT
0.8V OUT
/EN
DC-DC 4
VOUT
VFB
VIN
FPWM5
2MHz
INA196
I0.8V
WDI from main
processor
GPIO17
WDO
GPIO18
VMON13
TEMP IC
TEMP0.8V
TEMP IC
TEMP12V
POWER_GOOD
GPIO12
WARN_OC_0.8V_
OR_12V
GPIO13
SYSTEM RESET
GPIO14
OTHER
SEQUENCER DONE
(CASCADE INPUT)
GPIO17
I2C/
PMBUS
JTAG
V
4- wire Fan
12 V
4-
DC Fan
FPWM6
GPIO11
Fan Tach
25 kHz Fan PWM
12V
TACH
PWM
GND
5.1V
UCD90124A
www.ti.com SLVSAN8 –JANUARY 2012
APPLICATION INFORMATION
Figure 35. Typical Application Schematic
NOTE
Figure 35 is a simplified application schematic. Voltage dividers such as the ones placed
on VMON1 input have been ommited for simplifying the schematic. All VMONx pins which
are configured to measure a voltage that exceeds the 2.5V ADC reference are required to
have a voltage divider.
Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback 43
Product Folder Link(s) :UCD90124A