Datasheet

Delay
Delay
Delay
Power Good On
Power Good On
Power Good Off
POWER GOOD
SYSTEM RESET
configured without pulse
Pulse Pulse
SYSTEM RESET
configured with pulse
Power Good On
Delay
Delay or
GPI Tracking Release Delay
POWER GOOD
WDI
SYSTEM RESET
Watchdog
Start Time
Watchdog
Reset Time
Watchdog
Start Time
Watchdog
Reset Time
UCD90124A
SLVSAN8 –JANUARY 2012 www.ti.com
SYSTEM RESET SIGNAL
The UCD90124A can generate a programmable system-reset pulse as part of sequence-on. The pulse is created
by programming a GPIO to remain deasserted until the voltage of a particular rail or combination of rails reach
their respective POWER_GOOD_ON levels plus a programmable delay time. The system-reset delay duration
can be programmed as shown in Table 7. See an example of two SYSTEM RESET signals Figure 28. The first
SYSTEM RESET signal is configured so that it de-asserts on Power Good On and it asserts on Power Good Off
after a given common delay time. The second SYSTEM RESET signal is configured so that it sends a pulse after
a delay time once Power Good On is achieved. The pulse width can be configured between 0.001s to 32.256s.
See the UCD90xxx Sequencer and System Health Controller PMBus Command Reference for pulse width
configuration details.
Figure 28. System Reset with and without Pulse Setting
The system reset can react to watchdog timing. In Figure 29 The first delay on SYSTEM RESET is for the initial
reset release that would get a CPU running once all necessary voltage rails are in regulation. The watchdog is
configured with a Start Time and a Reset Time. If these times expire without the WDI clearing them then it is
expected that the CPU providing the watchdog signal is not operating. The SYSTEM RESET is toggled either
using a Delay or GPI Tracking Release Delay to see if the CPU recovers.
Figure 29. System Reset with Watchdog
Table 7. System-Reset Delay
Delay
0 ms
1 ms
2 ms
4 ms
8 ms
16 ms
32 ms
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