Datasheet

PMBUS_CNTRL PIN
RAIL 1 EN
RAIL 1 VOLTAGE
RAIL 2 EN
RAIL 2 VOLTAGE
POWER_GOOD_ON[1]
TON_DELAY [2]
TOFF_DELAY [1]
TOFF_DELAY [2]
Rail 1 andRail 2 arebothsequenced “ON” and
“OFF” bythePMBUS_CNTRL pinonly
Rail 2 hasRail 1 asan “ON” dependency
Rail 1 hasRail 2 asaFaultShutdownSlave
TON_DELAY [1]
VOUT_OV_FAULT _LIMIT
VOUT_UV_FAULT_LIMIT
MAX_GLITCH_TIME
TIMEBETWEEN
RESTARTS
MAX_GLITCH_TIME +
TOFF_DELAY[1]
MAX_GLITCH_TIME
TIMEBETWEEN
RESTARTS
Rail 1 issettousetheglitchfilterforUVorOVevents
Rail 1 issettoRESTART 3 timesafteraUVorOVevent
Rail 1 issettoshutdownwithdelayforaOVevent
TIMEBETWEEN
RESTARTS
MAX_GLITCH_TIME +
TOFF_DELAY[1]
MAX_GLITCH_TIME
TOFF_DELAY [1]
PMBUS_CNTRL PIN
RAIL 1 EN
RAIL 1 VOLTAGE
TON_MAX_FAULT_LIMIT[1]
RAIL 2 EN
RAIL 2 VOLTAGE
POWER_GOOD_ON[1]
TON_DELAY[2]
TON_DELAY[1]
TON_MAX_FAULT_LIMIT[1]
POWER_GOOD_ON[1]
TimeBetweenRestarts
Rail1andRail2arebothsequenced
“ON” and “OFF” bythePMBUS_CNTRL
pinonly
Rail2hasRail1asan “ON” dependency
Rail1issettoshutdownimmediately
andRESTART 1timeincaseofa Time
OnMaxfault
UCD90124A
SLVSAN8 –JANUARY 2012 www.ti.com
programmable warning levels (under and over) and two programmable fault levels (under and over). When any
monitored voltage goes outside of the warning or fault window, the PMBALERT# pin is asserted immediately,
and the appropriate bits are set in the PMBus status registers (see Figure 7). Detailed descriptions of the status
registers are provided in the UCD90xxx Sequencer and System Health Controller PMBus Command Reference
and the PMBus Specification.
A programmable glitch filter can be enabled or disabled for each MON input. A glitch filter for an input defined as
a voltage can be set between 0 and 102 ms with 400-μs resolution.
Fault-response decisions are based on results from the 12-bit ADC. The device cycles through the ADC results
and compares them against the programmed limits. The time to respond to an individual event is determined by
when the event occurs within the ADC conversion cycle and the selected fault response.
Figure 14. Sequencing and Fault-Response Timing
Figure 15. Maximum Turn-on Fault
The configurable fault limits are:
TON_MAX_FAULT – Flagged if a rail that is enabled does not reach the POWER_GOOD_ON limit within the
configured time
VOUT_UV_WARN – Flagged if a voltage rail drops below the specified UV warning limit after reaching the
POWER_GOOD_ON setting
VOUT_UV_FAULT – Flagged if a rail drops below the specified UV fault limit after reaching the
POWER_GOOD_ON setting
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