Datasheet

Comparators
Monitor
Inputs
12-bit
200ksps,
ADC
(0.5% Int. Ref)
SEQUENCING ENGINE
BOOLEAN
Logic Builder
JTAG
Or
GPIO
I2C/PMBus
FLASH Memory
User Data, Fault
and Peak Logging
13
6
64-pin QFN
22
General Purpose I/O
(GPIO)
Digital Inputs (8 max)
Digital Outputs (12 max)
Rail Enables (12 max)
Margining Outputs (10 max)
Multi-phase PWM (8 max)
Fan Control (4 max)
UCD90124A
SLVSAN8 –JANUARY 2012 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
FUNCTIONAL BLOCK DIAGRAM
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see
the TI Web site at www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
VALUE UNIT
Voltage applied at V33D to DV
SS
–0.3 to 3.8 V
Voltage applied at V33A to AV
SS
–0.3 to 3.8 V
Voltage applied to any other pin
(2)
–0.3 to (V33A + 0.3) V
Storage temperature (T
stg
) –40 to 150 °C
Human-body model (HBM) 2.5 kV
ESD rating
Charged-device model (CDM) 750 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to V
SS
THERMAL INFORMATION
UCD90124A
THERMAL METRIC
(1)
UNITS
RGC (64) PINS
θ
JA
Junction-to-ambient thermal resistance 26.4
θ
JC(top)
Junction-to-case(top) thermal resistance 21.2
θ
JB
Junction-to-board thermal resistance 1.7
°C/W
ψ
JT
Junction-to-top characterization parameter 0.7
ψ
JB
Junction-to-board characterization parameter 8.8
θ
JC(bottom)
Junction-to-case(bottom) thermal resistance 1.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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Product Folder Link(s) :UCD90124A