Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - system monitor Serialiser VQFN 64

Vmarg

Closed Loop

Margining

UCD90124A

VMON

GPIO

12V

V33FB

V33A

V33D

GPIO

3.3V OUT

VMON

1.8V OUT

3.3V_UCD

0.8V OUT

I0.8V

TEMP0.8V

VMON

I12V

TEMP12V

VMON

INA196

I12V

12V OUT

3.3V OUT

12V OUT

1.8V OUT

GPIO

0.8V OUT

PWM

2MHz

INA196

I0.8V

WDI from main

processor

GPIO

WDO

GPIO

TEMP IC

TEMP0.8V

TEMP IC

TEMP12V

POWER_GOOD

GPIO

WARN_OC_0.8V_

OR_12V

GPIO

SYSTEM RESET

GPIO

OTHER

SEQUENCER DONE

(CASCADE INPUT)

GPIO

I2C/

PMBUS

JTAG

/EN

DC-DC 1

VOUT

VFB

VIN

/EN

LDO1

VOUT

VIN

/EN

DC-DC 2

VOUT

VFB

VIN

4- wire Fan

12 V

DC Fan

PWM

GPIO

Fan Tach

25 kHz Fan PWM

12V

TACH

PWM

GND

5.1V

UCD90124A

www.ti.com

SLVSAN8 –JANUARY 2012

12-Rail Power Supply Sequencer and Monitor with ACPI Support and Fan Control

Check for Samples: UCD90124A

FEATURES

DESCRIPTION

The UCD90124A is a 12-rail PMBus/I

C addressable

• Monitor and Sequence 12 Voltage Rails

power-supply sequencer and monitor. The device

– All Rails Sampled Every 400 μs

integrates a 12-bit ADC for monitoring up to 12

– 12-bit ADC With 2.5-V, 0.5% Internal V

REF

power-supply voltage inputs. Twenty-six GPIO pins

can be used for power supply enables, power-on

– Sequence Based on Time, Rail and Pin

reset signals, external interrupts, cascading, or other

Dependencies

system functions. Twelve of these pins offer PWM

– Four Programmable Undervoltage and

functionality. Using these pins, the UCD90124A offers

Overvoltage Thresholds per Monitor

support for fan control, margining, and

• Nonvolatile Error and Peak-Value Logging per

general-purpose PWM functions.

Monitor (up to 12 Fault Detail Entries)

Specific power states can be achieved using the

• Closed-Loop Margining for 10 Rails

Pin-Selected Rail States feature. This feature allows

with the use of up to 3 GPIs to enable and disable

– Margin Output Adjusts Rail Voltage to

any rail. This is useful for implementing system

Match User-Defined Margin Thresholds

low-power modes and the Advanced Configuration

• Programmable Watchdog Timer and System

and Power Interface (ACPI) specification that is used

Reset

for hardware devices.

• Flexible Digital I/O Configuration

The TI Fusion Digital Power™ designer software is

• Pin-Selected Rail States

provided for device configuration. This PC-based

graphical user interface (GUI) offers an intuitive

• Multiphase PWM Clock Generator

interface for configuring, storing, and monitoring all

– Clock Frequencies From 15.259 kHz to

system operating parameters.

125 MHz

– Capability to Configure Independent Clock

Outputs for Synchronizing Switch-Mode

Power Supplies

• JTAG and I

C/SMBus/ PMBus™ Interfaces

APPLICATIONS

• Industrial / ATE

• Telecommunications and Networking

Equipment

• Servers and Storage Systems

• Any System Requiring Sequencing and

Monitoring of Multiple Power Rails

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PMBus, Fusion Digital Power are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (51 pages)

PAGE 1
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com 12-Rail Power Supply Sequencer and Monitor with ACPI Support and Fan Control Check for Samples: UCD90124A FEATURES DESCRIPTION • The UCD90124A is a 12-rail PMBus/I2C addressable power-supply sequencer and monitor. The device integrates a 12-bit ADC for monitoring up to 12 power-supply voltage inputs. Twenty-six GPIO pins can be used for power supply enables, power-on reset signals, external interrupts, cascading, or other system functions.
PAGE 2
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com RECOMMENDED OPERATING CONDITIONS Supply voltage during operation (V33D, V33DIO, V33A) MIN NOM MAX 3 3.3 3.6 V 110 °C 125 °C –40 Operating free-air temperature range, TA Junction temperature, TJ UNIT ELECTRICAL CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT SUPPLY CURRENT IV33A VV33A = 3.3 V 8 mA IV33DIO VV33DIO = 3.3 V 2 mA VV33D = 3.
PAGE 4
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT 15.260 125000 kHz 0.001 7800 0 100 MARGINING OUTPUTS TPWM_FREQ MARGINING-PWM frequency FPWM1-8 PWM3-4 DUTYPWM MARGINING-PWM duty cycle range % SYSTEM PERFORMANCE VDDSlew Minimum VDD slew rate VDD slew rate between 2.3 V and 2.
PAGE 5
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com PMBus/SMBus/I2C The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus and PMBus is shown below. I2C/SMBus/PMBus TIMING REQUIREMENTS TA = –40°C to 85°C, 3 V < VDD < 3.6 V; typical values at TA = 25°C and VCC = 2.
PAGE 6
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com DEVICE INFORMATION Figure 3.
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UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com Table 1. PIN FUNCTIONS (continued) PIN NAME PIN NO. I/O TYPE MON9 63 I DESCRIPTION Analog input (0 V–2.5 V) MON10 50 I Analog input (0 V–2.5 V) MON11 52 I Analog input (0 V–2.5 V) MON12 54 I Analog input (0 V–2.5 V) MON13 56 I Analog input (0 V–2.
PAGE 8
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com Table 1. PIN FUNCTIONS (continued) PIN NAME PIN NO. I/O TYPE DESCRIPTION INPUT POWER AND GROUNDS RESET 9 Active-low device reset input. Hold low for at least 2 μs to reset the device. V33FB 58 3.3-V linear regulator feedback connection. Leave unconnected. V33A 46 Analog 3.3-V supply. Refer to the layout guidelines section. V33D 45 Digital core 3.3-V supply. Refer to the layout guidelines section. V33DIO1 7 Digital I/O 3.3-V supply.
PAGE 9
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com THEORY OF OPERATION Modern electronic systems often use numerous microcontrollers, DSPs, FPGAs, and ASICs. Each device can have multiple supply voltages to power the core processor, analog-to-digital converter or I/O. These devices are typically sensitive to the order and timing of how the voltages are sequenced on and off.
PAGE 10
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com Figure 4.
PAGE 11
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com • or disabled Other rails to turn off in case of a fault on a rail (fault-shutdown slaves) Figure 5. Fusion GUI VOUT-Config Tab The Synchronize margins/limits/PG to Vout checkbox is an easy way to change the nominal operating voltage of a rail and also update all of the other limits associated with that rail according to the percentages shown to the right of each entry.
PAGE 12
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com The Fusion GUI Monitor page has a number of options, including a device dashboard and a system dashboard, for viewing and controlling device and system status. Figure 6. Fusion GUI Monitor Page The UCD90124A also has status registers for each rail and the capability to log faults to flash memory for use in system troubleshooting. This is helpful in the event of a power-supply or system failure.
PAGE 13
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com Figure 7.
PAGE 14
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com Figure 8. Fusion GUI Flash-Error Log (Logged Faults) POWER-SUPPLY SEQUENCING The UCD90124A can control the turn-on and turn-off sequencing of up to 12 voltage rails by using a GPIO to set a power-supply enable pin high or low. In PMBus-based designs, the system PMBus master can initiate a sequence-on event by asserting the PMBUS_CNTRL pin or by sending the OPERATION command over the I2C serial bus.
PAGE 15
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.
PAGE 16
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com PIN SELECTED RAIL STATES This feature allows with the use of up to 3 GPIs to enable and disable any rail. This is useful for implementing system low-power modes and the Advanced Configuration and Power Interface (ACPI) specification that is used for operating system directed power management in servers and PCs. In up to 8 system states, the power system designer can define which rails are on and which rails are off.
PAGE 17
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com VOLTAGE MONITORING Up to 12 rail voltages can be monitored using the analog input pins. The input voltage range is 0 V–2.5 V for MON pins 1-6, 59, 62 and 63. Pins 50, 52, 54 and 56 can measure down to 0.2 V. Any voltage between 0 V and 0.2 V on these pins is read as 0.2 V. External resistors can be used to attenuate voltages higher than 2.5 V. The ADC operates continuously, requiring 3.89 μs to convert a single analog input.
PAGE 18
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com IOUT_CAL_GAIN is a PMBus command that allows the scale factor of an external current sensor and any amplifiers or attenuators between the current sensor and the MON pin to be entered by the user in milliohms. IOUT_CAL_OFFSET is the current that results in 0 V at the MON pin. The combination of these PMBus commands allows current to be reported in amperes. The example below using the INA196 would require programming IOUT_CAL_GAIN to Rsense(mΩ)×20.
PAGE 19
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com TMP20 UCD90124A MONx VOUT AVSS1 GND 3.3V V+ Vout = -11.67mV/°C x T + 1.8583 at -40°C < T < 85°C Figure 12. Remote Temperature Monitoring Circuit Example Using the TMP20 TEMPERATURE BY HOST INPUT If the host system has the option of not using the temperature-sensing capability of the UCD90124A, it can still provide the desired temperature to the UCD90124A through PMBus.
PAGE 20
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com programmable warning levels (under and over) and two programmable fault levels (under and over). When any monitored voltage goes outside of the warning or fault window, the PMBALERT# pin is asserted immediately, and the appropriate bits are set in the PMBus status registers (see Figure 7). Detailed descriptions of the status registers are provided in the UCD90xxx Sequencer and System Health Controller PMBus Command Reference and the PMBus Specification.
PAGE 21
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com VOUT_OV_WARN – Flagged if a rail exceeds the specified OV warning limit at any time during startup or operation VOUT_OV_FAULT – Flagged if a rail exceeds the specified OV fault limit at any time during startup or operation MAX_TOFF_WARN – Flagged if a rail that is commanded to shut down does not reach 12.5% of the nominal rail voltage within the configured time Faults are more serious than warnings.
PAGE 22
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com fault-shutdown slaves sequence-off, the UCD90124A waits for a programmable delay time between 0 and 1275 ms in increments of 5 ms and then sequences-on the faulted rail and fault-shutdown slaves according to the start-up sequence configuration. This is repeated until the faulted rail and fault-shutdown slaves successfully achieve regulation or for a user-selected 1, 2, 3, or 4 times.
PAGE 23
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com Table 4.
PAGE 24
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com GPO Dependencies GPIOs can be configured as outputs that are based on Boolean combinations of up to two ANDs all ORed together (Figure 16). Inputs to the logic blocks can include the first 8 defined GPOs, GPIs and rail-status flags. One rail status type is selectable as an input for each AND gate in a Boolean block. For a selected rail status, the status flags of all active rails can be included as inputs to the AND gate.
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UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com Table 5.
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UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com 3ms 3ms 3ms 3ms GPI GPO 1ms Figure 19. GPO Behavior When Ignoring Inputs During Delay State Machine Mode Enable When this bit within the GPO_CONFIG command is set, only one of the AND path will be used at a given time. When the GPO logic result is currently TRUE, AND path 0 will be used until the result becomes FALSE. When the GPO logic result is currently FALSE, AND path 1 will be used until the result becomes TRUE.
PAGE 27
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com A shutdown on one or more of the master rails can initiate shutdowns of the slave devices. The master shutdowns can be initiated intentionally or by a fault condition. This method works to coordinate multiple controllers, but it does not enforce interdependency between rails within a single controller. The PMBus specification implies that the power-good signal is active when ALL the rails in a controller are regulating at their programmed voltage.
PAGE 28
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com To determine the closest frequency to 1MHz that PWM3 can be set to calculate as the following: 1. 2. 3. 4. Divide 15.625MHz by 1MHz to obtain 15.625. Round off 15.625 to obtain an integer of 16. Divide 15.625MHz by 16 to obtain actual closest frequency of 976.563kHz. Use Equation 2 to determine duty cycle resolution to obtain 6.25% duty cycle resolution. All frequencies below 238Hz will have a duty cycle resolution of 0.0015%.
PAGE 29
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com MON(1:12) 3.3V UCD90124A POWER SUPPLY 10k W GPIO(1:12) /EN 3.3V Vout VOUT VFB Rmrg_HI V FB GPIO GPIO “0” or “1” VOUT “0” or “1” Rmrg_LO 3. 3V POWER SUPPLY 10k W /EN Vout VOUT VFB VFB Rmrg_HI VOUT . 3.3V Rmrg_LO Open Loop Margining Figure 21. Open-Loop Margining Closed-Loop Margining Closed-loop margining uses a PWM or FPWM output for each power supply that is being margined.
PAGE 30
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com voltage for the fan. The negative input of the fan is connected to the collector or drain of a transistor. The transistor is turned off and on using a GPIO pin. Four-wire fans can be controlled the same way. However, four-wire fans should use the fan PWM input (the fourth wire). It can be driven directly by one of the eight FPWM or the two adjustable PWM outputs.
PAGE 31
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com Temperature sensor MONx AVSS3 44-wire Fan 12 V UCD90124A FPWM GPIO 15kHz – 30kHz 3.3V PWM signal changes fan speed with duty cycle 12V PWM TACH 3.3V TACH output to GPI/GPIO for fan speed monitoring DC Fan GND Figure 25. Four-Wire Fan Connection The UCD90124A autocalibrate feature automatically finds and records the turn-on, turn-off and maximum speeds and duty cycles for any fan.
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UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com TOT Inputs: TON, TOFF, TOT, Update Interval, Rail where MEAS_TEMP is monitored, GPOx pin • System starts up at t = 0 seconds • MEAS_TEMP = 25°C → ambient temp • GPO/PWM is low and Fan is off • Check MEAS_TEMP every 1 second (or 250 msec) • When MEAS_TEMP = TON, set GPO/PWM = 1 → turn fan on • Leave GPO/PWM = 1 unless MEAS_TEMP < TOFF • If MEAS_TEMP is > TON, declare a fault and take the prescribed action.
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UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com TOT TEMP5, SPD5 TEMP4, SPD4 TEMP3, SPD3 Inputs: TOT, Updates Interval, Rail that MEAS_TEMP TEMP2, SPD2 MEAS_TEMP is being monitored on, PWM pin, PWM freq, PWM temp rate, FANTAC TEMP1, SPD1 pin, 5x (TEMPn, SPEEDn) setpoints.
PAGE 34
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com SYSTEM RESET SIGNAL The UCD90124A can generate a programmable system-reset pulse as part of sequence-on. The pulse is created by programming a GPIO to remain deasserted until the voltage of a particular rail or combination of rails reach their respective POWER_GOOD_ON levels plus a programmable delay time. The system-reset delay duration can be programmed as shown in Table 7. See an example of two SYSTEM RESET signals Figure 28.
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UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com Table 7. System-Reset Delay (continued) Delay 64 ms 128 ms 256 ms 512 ms 1.02 s 2.05 s 4.10 s 8.19 s 16.38 s 32.8 s WATCH DOG TIMER A GPI and GPO can be configured as a watchdog timer (WDT). The WDT can be independent of power-supply sequencing or tied to a GPIO functioning as a watchdog output (WDO) that is configured to provide a system-reset signal. The WDT can be reset by toggling a watchdog input (WDI) pin or by writing to SYSTEM_WATCHDOG_RESET over I2C.
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UCD90124A SLVSAN8 – JANUARY 2012 WDI www.ti.com
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UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com UCD90124A B340A 3.3V C V33A AVSS1 V33D AVSS2 V33DIO1 AVSS3 V33DIO2 DVSS1 DVSS2 DVSS3 Figure 31. Brownout Circuit PMBUS ADDRESS SELECTION Two pins are allocated to decode the PMBus address. At power up, the device applies a bias current to each address-detect pin, and the voltage on that pin is captured by the internal 12-bit ADC. The PMBus address is calculated as follows.
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UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com Table 10. PMBus Address Assignment Rules (continued) Address STATUS 11 Avoid 12 Prohibited 13-125 Available 126 For JTAG Use 127 Prohibited Reason Causes conflicts with other devices during program flash updates. PMBus alert response protocol Default value; may cause conflicts with other devices. Used by TI manufacturing for device tests.
PAGE 39
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com Figure 33. Fusion GUI PMBus Configuration Script Export Tool 3. Another in-circuit programming option is for the Fusion GUI to create a data flash image from the configuration file (Figure 34). The configuration files can be exported in Intel Hex, Serial Vector Format (SVF) and S-record. The image file can be downloaded into the device using I2C or JTAG. The Fusion GUI tools can be used on-board if the Fusion GUI can gain ownership of the target board I2C bus.
PAGE 40
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com Figure 34. Fusion GUI Device Configuration Export Tool Devices can be programmed off-board using the Fusion GUI tools or a dedicated device programmer. For small runs, a ZIF socketed board with an I2C header can be used with the standard Fusion GUI or manufacturing GUI. The TI Evaluation Module for UCD90xxx 64-pin Sequencer and System Health Monitor (UCD90SEQEVM64-650) can be used for this purpose.
PAGE 41
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com Table 11. Configuration Options Data Flash via JTAG Data Flash via I2C PMBus Commands via I2C Data Flash Export (.svf type file) Data Flash Export (.
PAGE 42
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com INTERNAL FAULT MANAGEMENT AND MEMORY ERROR CORRECTION (ECC) The UCD90124A verifies the firmware checksum at each power up. If it does not match, then the device waits for I2C commands but does not execute the firmware. A device configuration checksum verification is also performed at power up. If it does not match, the factory default configuration is loaded. The PMBALERT# pin is asserted and a flag is set in the status register.
PAGE 43
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com APPLICATION INFORMATION 12V 12V OUT TEMP IC 3.3V_UCD I12V TEMP12V INA196 12V OUT 5V OUT 3.3V OUT 2.5V OUT 1.8V OUT 1.5V OUT 1.2V OUT 0.8V OUT I0.8V TEMP0.8V I12V TEMP12V V33A V33D V33FB 5.1V VIN GPIO1 /EN VMON1 VMON2 VMON3 VMON4 VMON5 VMON6 VMON7 VMON8 VMON9 VMON10 VMON11 VMON12 DC-DC 1 VFB VIN GPIO2 /EN DC-DC 2 VFB GPIO4 VIN /EN GPIO5 2.5V OUT VOUT DC-DC 3 VIN VFB /EN VOUT 1.
PAGE 44
UCD90124A SLVSAN8 – JANUARY 2012 www.ti.com Layout guidelines The thermal pad provides a thermal and mechanical interface between the device and the printed circuit board (PCB). Connect the exposed thermal pad of the PCB to the device VSS pins and provide at least a 4 × 4 pattern of PCB vias to connect the thermal pad and VSS pins to the circuit ground on other PCB layers. For supply-voltage decoupling, provide power-supply pin bypass to the device as follows: • 0.1-μF, X7R ceramic in parallel with 0.
PAGE 45
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UCD90124ARGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 UCD90124ARGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 UCD90124ARGCT VQFN RGC 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.
PAGE 47
PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCD90124ARGCR VQFN RGC 64 2000 367.0 367.0 38.0 UCD90124ARGCT VQFN RGC 64 250 210.0 185.0 35.0 UCD90124ARGCT VQFN RGC 64 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.