Datasheet

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VIT−
10%
90%
INPUT
OUTPUT
VIT+
t
D1
t
F
t
F
t
D2
UCD8220
SLUS652D – MARCH 2005 – REVISED OCTOBER 2006
ELECTRICAL CHARACTERISTICS (continued)
V
DD
= 12 V, 4.7-F capacitor from V
DD
to AGND, 1 µ F from PVDD to PGND, 0.22-F capacitor from 3V3 to AGND,
T
A
= T
J
= -40C to 105C, (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CLF output high level CS > ILIM , I
LOAD
= -7 mA 2.64 - -
V
CLF output low level CS ≤ ILIM, I
LOAD
= 7 mA - - 0.66
Propagation delay from CLK to CLF CLK rising to CLF falling after a current limit event - 15 25 ns
CURRENT SENSE COMPARATOR
Bias voltage Includes CS comp offset 5 25 50 mV
Input bias current - – 1 - µ A
Propagation delay from CS to OUTx ILIM = 0.5 V, measured on OUTx, CS = threshold + 60 mV - 25 40
ns
Propagation delay from CS to CLF ILIM = 0.5 V, measured on CLF, CS = threshold + 60 mV - 25 50
CURRENT SENSE DISCHARGE TRANSISTOR
Discharge resistance CLK = low, resistance from CS to AGND 10 35 75 Ω
OUTPUT DRIVERS
Source current
(2)
V
DD
= 12 V, CLK = high, OUTx = 5 V - 4 -
Sink current
(2)
V
DD
= 12 V, CLK = low, OUTx = 5 V - 4 -
A
Source current
(2)
V
DD
= 4.75 V, CLK = high, OUTx = 0 - 2 -
Sink current
(2)
V
DD
= 4.75 V, CLK = low, OUTx = 4.75 V - 3 -
Rise time, t
R
C
LOAD
= 2.2 nF, V
DD
= 12 V - 10 20
ns
Fall time, t
F
C
LOAD
= 2.2 nF, V
DD
= 12 V - 10 15
Output with V
DD
< UVLO V
DD
= 1.0 V, I
SINK
= 10 mA - 0.8 1.2 V
C
LOAD
= open, V
DD
= 12 V, CLK rising, t
D1
- 25 35
Propagation delay from CLK to OUTx ns
C
LOAD
= open, V
DD
= 12 V, CLK falling, t
D2
25 35
(2) Ensured by design. Not 100% tested in production.
Figure 3. Timing Diagram
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