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CS
(9)
+
-
3V3
+
OUT
ON OFF
S1
S2
R
R
CTRL
(6)
ISET
(4)
R_ISET
PWM
0.25V
C
12pF
int
I_SC=1.85/(11xR_ISET)
TOCLEAR
of
PWMLATCH
10.0
1.0
0.1
0.01
10
3
10
6
10
5
10
4
R
ISET
− Resistance − Ω
R
ISET
− Slope − V/µs
11xR_ISETx12
V/ sm
6
1.85x10
SLOPE=
(3)
UCD8220
SLUS652D – MARCH 2005 – REVISED OCTOBER 2006
Selecting the ISET Resistor for Peak Current
Mode Control with Internal Slope Compensation
Figure 35. UCCD8220 Configured in Peak Current
Control with Internal Slope Compensation
Figure 36. Slope vs RISET Resistance
When the ISET resistor is configured as shown in
Figure 35 with the ISET resistor connected between
The amount of slope compensation required depends
the ISET pin and AGND, the device is configured for
on the design of the power stage and the output
peak current mode control with internal slope
specifications. A general rule is to add an up-slope
compensation. The voltage at the ISET pin is 1.85
equal to the down slope of the output inductor. Refer
volts so the internal slope compensation current,
to References 6 and 7 for a more detailed discussion
I_SC, being fed into the internal slope compensation
regarding slope cpmpensation in peak current mode
capacitor is equal to 1.85 / (11x R_ISET). The voltage
controlled pwer stages.
slope at the PWM comparator input which is
generated by this current is equal to:
Handshaking
The UCD8220 has a built-in handshaking feature to
facilitate efficient start-up of the digitally managed
power supply. At start-up the CLF flag is held high
until all the internal and external supply voltages of
the UCD8220 is within its operating range. Once the
supply voltages are within acceptable limits, the CLF
goes low and the device processes the CLK signals.
The digital controller should monitor the CFL flag at
start-up and wait for the CLF flag to go LOW before
sending CLK pulses to the UCD8K device.
Driver Output
The high-current output stage of the UCD8220 is
capable of supplying 4-A peak current pulses and
swings to both PVDD and PGND.
The drive output uses the Texas Instruments
TrueDrive™ architecture, which delivers rated current
into the gate of a MOSFET when it is most needed,
during the Miller plateau region of the switching
transition providing efficiency gains.
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