Datasheet

www.ti.com
APPLICATION INFORMATION
UCD8220
SLUS652D – MARCH 2005 – REVISED OCTOBER 2006
The pulse train uses a Texas Instruments
Introduction
communication protocol which is a proprietary
The UCD8220 is a digitally managed analog PWM communication system that provides handles for
controller configured with push-pull drive logic. control of the power supply operation through
software programming. The rising edge of the CLK
In systems using the UCD8220 device, the PWM
signal represents the switching frequency. Figure 30
feedback loop is closed using the traditional analog
depicts the operation of the UCD8220 in one of 5
methods, but the UCD8220 includes circuitry to
modes. At the time when the internal signal REF OK
interpret a time-domain digital pulse train from a
is low, the UCD8220 is not ready to accept CLK
digital controller. The pulse train contains the
inputs. Once the REF OK signal goes high, then the
operating frequency and maximum duty cycle limit
device is ready to process inputs. While the CLK
and hence controls the power supply operation. This
input is low, the outputs are disabled and the CLK
eases implementing a converter with high-level
signal is used as an enable input. Once the Digital
control features without the added complexity or
controller completes its initialization routine and
digital PWM resolution limitations encountered when
verifies that all voltages are within their operating
closing the voltage control loop in the discrete time
range, then it starts the soft-start procedure by slowly
domain.
ramping up the duty cycle of the CLK signal, while
maintaining the desired switching frequency. The
The UCD8220 can be configured for either peak
CLK duty cycle continues to increase until it reaches
current mode or voltage mode control. It provides a
steady-state where the analog control loop takes over
programmable current limit function and a digital
and regulates the output voltage to the desired set
output current limit flag which can be monitored by
point. During steady state, the duty cycle of the CLK
the host controller. For fast switching speeds, the
pulse can be set using a volt second product
output stages use the TrueDrive™ output
calculation in order to protect the primary of the
architecture, which delivers rated current of 4 A into
power transformer from saturation during transients.
the gate of a MOSFET during the Miller plateau
region of the switching transition. Finally they also
When the power supply enters current limit, the
include a 3.3-V, 10-mA linear regulator to provide
outputs are quickly turned off, and the CLF signal is
power for the digital controller.
set high in order to notify the digital controller that the
last power pulse was truncated because of an
The UCD8220 includes circuitry and features to ease
overcurrent event. The benefit of this technique is in
implementing a converter that is managed by a
the flexibility it offers.
microcontroller or a digital signal processor. Digitally
managed power supplies provide software
The software is now in charge of the response to
programmability and monitoring capability of a power
overcurrent events. In typical analog designs, the
supply's operation including:
power supply response to overcurrent is hardwired in
• Switching frequency
the silicon. With this method, the user can configure
• Synchronization
the response differently for different applications. For
example, the software can be configured to latch-off
• D
MAX
the power supply in response the first overcurrent
• V x S clamp
event, or to allow a fixed number of current limit
• Input UVLO start/stop voltage
events, so that the supply is capable of starting up
• Input OVP start/stop voltage
into a capacitive load. The user can also configure
the supply to enter into hiccup mode immediately or
• Soft-start profile
after a certain number of current limit events. As
• Current limit operation
described later in this data sheet, the current limit
• Shutdown
threshold can be varied in time to create unique
• Temperature shutdown
current limit profiles. For example, the current limit set
point can be set high for a predefined number of
CLK Input Time-Domain Digital Pulse Train
cycles to blow a manual fuse, and can be reduced
down to protect the system in the event of a faulty
While the loop is closed in the analog domain, the
fuse.
UCD8220 is managed by a time-domain digital pulse
train from a digital controller. The pulse train, shown
as CLK in Figure 30 , contains the operating
frequency and maximum duty cycle limit and hence
controls the power supply operation as listed above.
Copyright © 2005 – 2006, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s): UCD8220