Datasheet

UCD7242
SLUS962B –JANUARY 2010–REVISED AUGUST 2012 www.ti.com
PIN FUNCTIONS
UCD7242 –BUCK POWER STAGE
QFN PIN NAME I/O FUNCTION
High impedance digital input capable of accepting 3.3V or 5 V logic level signals up to 2 MHz. A
Schmitt trigger input comparator desensitizes this pin from external noise. This pin controls the state of
the high side MOSFET and the low side MOSFET when SRE-B is high.
1 PWM-B I
PWM = high PWM = low PWM = 1.65 V
SRE = high HS = on, LS = off HS = off, LS = on HS = off, LS = off
SRE = low HS = on, LS = off HS = off, LS = off HS = off, LS = off
Synchronous Rectifier Enable input for the B-channel. High impedance digital input capable of
2 SRE-B I accepting 3.3V or 5V logic level signals used to control the synchronous rectifier switch. An appropriate
anti-cross-conduction delay is used during synchronous mode.
Connection for the B-channel charge pump capacitor that provides a floating supply for the high side
3 BST_B I
driver. Connect a 0.22μF ceramic capacitor from this pin to BSW-B (pin 4).
4 BSW-B I Connection for B-channel charge pump capacitor. Internally connected to SW-B.
Gate drive voltage for the power MOSFETs. For V
IN
≥ 4.75V, the internal V
GG
generator can be used.
For V
IN
< 4.75 V, this pin should be driven from an external bias supply. When externally driven,
5 V
GG
I/O
V
GG
_DIS must be tied to V
GG
. In all cases, bypass this pin with a 4.7μF (min), 10V (min) ceramic
capacitor to PGND.
When tied to V
GG
, disables the on-chip V
GG
generator to allow gate drive voltage to be supplied from
6 V
GG
_DIS I an external source. This is required when V
IN
is < 4.75V. To use the internal V
GG
generator, tie to
GND.
MOSFET current sense monitor output. Provides a current source output that is proportional to the
7 IMON-B O current flowing in the power MOSFETs. The gain on this pin is equal to 20μA/A. The I
MON
pin should
be connected to a resistor to GND to produce a voltage proportional to the power-stage load current.
8 testmode I Test mode only. Tie to GND.
Fault flag for the B-channel. This signal is a 3.3V digital output which is latched high when the current
in the B-channel high-side FET exceeds the current limit trip point. When tripped, high-side FET drive
pulses are truncated to limit output current. FLT is cleared after one complete switching cycle without a
9 FLT-B O
fault. Additionally, if the die temperature exceeds 170°C, the temperature sensor will initiate a thermal
shutdown that halts output switching and sets the FLT flag. Normal operation resumes when the die
temperature falls below the thermal hysteresis band.
10, 12, 15, 17 PGND – Shared power ground return for the buck power stage
11, 16 NC – No internal connection. It is recommended that these pins be tied to PGND.
Switching node of the B-channel buck power stage and square wave input to the buck inductor.
13 SW-B –
Electrically this is the connection of the high side MOSFET source to the low side MOSFET drain.
Switching node of the A-channel buck power stage and square wave input to the buck inductor.
14 SW-A –
Electrically this is the connection of the high side MOSFET source to the low side MOSFET drain.
Fault flag for the A-channel. This signal is a 3.3V digital output which is latched high when the current
in the A-channel high-side FET exceeds the current limit trip point. When tripped, high-side FET drive
pulses are truncated to limit output current. FLT is cleared after one complete switching cycle without a
18 FLT-A O
fault. Additionally, if the die temperature exceeds 170°C, the temperature sensor initiates a thermal
shutdown that halts output switching and sets the FLT flag. Normal operation resumes when the die
temperature falls below the thermal hysteresis band.
Temperature sense pin. The voltage on this pin is proportional to the die temperature. The gain is
10mV/°C. At T
J
= 0°C, the output voltage has an offset of 0.47V. When the die temperature reaches
19 TMON O the thermal shutdown threshold, this pin is pulled to BP3 and the power FETs are switched off. When
the die temperature falls below the thermal hysteresis band, the FLT flag clears and normal operation
resumes.
MOSFET current sense monitor output. Provides a current source output that is proportional to the
20 IMON -A O current flowing in the power MOSFETs. The gain on this pin is equal to 20μA/A. The IMON pin should
be connected to a resistor to GND to produce a voltage proportional to the power-stage load current.
21 GND – Analog ground return.
Output of internal 3.3V LDO regulator for powering internal logic circuits. Bypass this pin with 1μF
22 BP3 O
(min) to GND. This LDO is supplied by the V
GG
pin.
23 BSW-A – Connection for A-channel charge pump capacitor. Internally connected to SW-A.
Connection for the A-channel charge pump capacitor that provides a floating supply for the high side
24 BST-A –
driver. Connect a 0.22μF ceramic cap from this pin to BSW-A (pin 23).
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