Datasheet

UCD7242
SLUS962B –JANUARY 2010–REVISED AUGUST 2012 www.ti.com
ELECTRICAL CHARACTERISTICS
V
IN
= 12V; 1μF from BP3 to GND, 0.22μF from BST to BSW, 4.7μF from V
GG
to PGND, T
A
= T
J
= –40°C to 125°C (unless
otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SUPPLY SECTION
Outputs not switching, V
IN
= 2.2 V, 6 mA
PWM(INH) = LOW, SRE(INL) = HIGH,
V
GG
_DIS = HIGH, V
GG
= 5V
Supply current
Outputs not switching, V
IN
= 18 V, 6 mA
PWM(INH) = LOW, SRE(INL) = HIGH,
V
GG
_DIS = LOW
GATE DRIVE UNDER VOLTAGE LOCKOUT
V
GG
UVLO ON BP3 Rising 4.0 V
UVLO OFF BP3 Falling 3.8 V
UVLO hysteresis 200 mV
V
GG
SUPPLY GENERATOR
V
GG
V
IN
= 7 to 18 V 5.2 6.25 6.8 V
V
GG
drop out V
IN
= 4.75 to 7 V, I
VGG
< 50 mA 600 mV
BP3 SUPPLY VOLTAGE
BP3 I
DD
= 0 to 10 mA 3.15 3.3 3.45 V
INPUT SIGNAL (PWM, SRE)
V
IH
Positive-going input threshold voltage 2.1 2.3 V
V
IL
Negative-going input threshold voltage 1 1.2 V
3-state Condition 1.4 1.9 V
t
HLD_R
3-state hold-off time V
PWM
= 1.65 V 275 ns
V
PWM
= 5.0 V 133
I
PWM
Input current V
PWM
= 3.3 V 66 μA
V
PWM
= 0 V –66
V
SRE
= 5.0 V 1
I
SRE
Input current V
SRE
= 3.3 V 1 μA
V
SRE
= 0 V 1
V
GG
DISABLE (V
GG
_DIS)
Input resistance to AGND V
GG
_DIS 50 100 150 kΩ
Threshold 1.35 1.6 V
Hysteresis 550 mV
FAULT FLAG (FLT)
FLT Output High Level I
OH
= 2 mA 2.7 V
FLT Output Low Level I
OL
= –2 mA 0.6 V
CURRENT LIMIT
Over current threshold 14.5 15 15.5 A
T
fault_HS
delay until HS FET off
(1)
80 ns
T
fault_FF
delay until FLT asserted
(1)
100 ns
Propagation delay from PWM to reset FLT
(1)
1
st
falling edge of PWM without a fault event 100 ns
High side blanking time
(1)
Over currents during this period will not be detected 60 ns
CURRENT SENSE AMPLIFIER
Gain I
MON
/ I
OUT
, (see Figure 14 ) 19 20 21 μA/A
Bandwidth
(1)
5 kHz
(1) As designed and characterized. Not 100% tested in production.
4 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: UCD7242