Datasheet
47uF
Vout1
GND
22uF 25V
330uF
+
PWM1
SRE1
FF1
CS1
Temp
EAp1
EAn1
10r0
10r0
800nH
800nH
0.22uF
22uF 25V
0.22uF
4.7uF
1uF
4k99
26
25
18
20
1
2
9
7
19
5
8
29
28
27
14
24
23
15
16
17
30
31
PWM-A
SRE-A
FLT-A
IMON-A
PWM-B
SRE-B
FLT-B
IMON-B
TMON
V
GG
DIS
Test
Vin
NC
SW-A
BST-A
BSW-A
PGND
NC
PGND
Vin
Vin
NC
Vin
32
13
3
4
10
11
12
6
SW-B
BST-B
BSW-B
PGND
NC
PGND
V
GG
22 V
DD
21 AGND
UCD7242
Vin
+
330uF
SN74LVC1G32
UCD7242
SLUS962B –JANUARY 2010–REVISED AUGUST 2012
www.ti.com
Figure 18. 20A Design
Layout Recommendations
The primary thermal cooling path is from the V
IN
, GND, and the SW “stripes” on the bottom of the package. Wide
copper traces should connect to these nodes. 1-ounce copper should be the minimum thickness of the top layer;
however, 2-ounce copper is better. Multiple thermal vias should be placed near the GND stripes that connect to a
PCB ground plane. There is room to place multiple 10-mil (0.25mm) diameter vias next to the V
IN
and GND
stripes under the package.
For input bypassing, the 22µF input ceramic capacitors should be connected as close as possible to the V
IN
and
GND stripes. If possible, the input caps should be placed directly under the UCD7242 using multiple 10-mil vias
to bring the V
IN
and GND connections to the back side of the board. Minimizing trace inductance in the bypass
path is extremely important to reduce the amplitude of ringing on the switching node.
24 Submit Documentation Feedback Copyright © 2010–2012, Texas Instruments Incorporated
Product Folder Links: UCD7242