Datasheet

UCD7242
SLUS962B –JANUARY 2010–REVISED AUGUST 2012 www.ti.com
DETAILED DESCRIPTION
PWM INPUT
The PWM input pin accepts the digital signal from the controller that represents the desired high-side FET on
time. This input is designed to accept 3.3V logic levels, but is also tolerant of 5V input levels. The SRE pin sets
the behavior of the PWM pin. When the SRE pin is asserted high, the device is placed in synchronous mode. In
this mode, the timing duration of the high-side gate drive and the low-side gate drive are both controlled by the
PWM input signal. When PWM is high, the high-side MOSFET is on and the low-side MOSFET is off. When
PWM is low, the high-side MOSFET is off and the low-side MOSFET is on. An optimized anti-cross-conduction
delay is introduced to ensure the proper FET is turned off before the other FET is turned on. When the SRE pin
is asserted low, the device is placed in non-synchronous mode. In this mode the PWM input only controls the
high-side MOSFET. When PMW is high, the high-side MOSFET is on. The low side FET is always held off.
The PWM input supports a 3-state detection feature. It can detect if the PWM input signal has entered a 3-state
mode. When 3-state mode is detected, both the high-side and low-side MOSFETs are held off. To support this
mode, the PWM input pin has an internal pull-up resistor of approximately 50kΩ to 3.3V and a 50kΩ pull-down
resistor to ground. During normal operation, the PWM input signal swings below 0.8V and above 2.5V. If the
source driving the PWM pin enters a 3-state or high impedance state, the internal pull-up/pull down resistors will
tend to pull the voltage on the PWM pin to 1.65V. If the voltage on the PWM pin remains within the 0.8V to 2.5V
3-state detection band for longer than t
HLD_R
, 3-state detection hold-off time, then the device enters 3-state mode
and turns both MOSFETs off. This behavior occurs regardless of the state of the SRE pin. When exiting 3-state
mode, PWM should first be asserted low and SRE High. This ensures that the bootstrap capacitor is recharged
before attempting to turn on the high-side FET. The logic threshold of this pin typically exhibits 900mV of
hysteresis to provide noise immunity and ensure glitch-free operation.
SRE INPUT
The SRE (Synchronous Rectifier Enable) pin is a high impedance digital input. It is designed to accept 3.3V logic
levels, but is also tolerant of 5V levels. When asserted high, the operation of the low-side synchronous rectifier
FET is enabled. The state of the low-side MOSFET is governed by the PWM input. When SRE is asserted low,
the low-side FET is continuously held low, keeping the FET off. While held off, current flow in the low-side FET is
restricted to its intrinsic body diode. The logic threshold of this pin typically exhibits 900mV of hysteresis to
provide noise immunity and ensure glitch-free operation.
V
IN
V
IN
supplies power to the internal circuits of the device. The input power is conditioned by an internal linear
regulator that provides the V
GG
gate drive voltage. A second regulator that operates off of the V
GG
rail produces
an internal 3.3V supply that powers the internal analog and digital functional blocks. The V
GG
regulator produces
a nominal 6.2V. The output of the V
GG
regulator is monitored by the Under-Voltage Lock Out (UVLO) circuitry.
The device will not attempt to produce gate drive pulses until the V
GG
voltage is above the UVLO threshold. This
ensures that there is sufficient voltage available to drive the power FETs into saturation when switching activity
begins. To use the internal V
GG
regulator, V
IN
should be at least 4.7V. When performing power conversion with
V
IN
values less than 4.7V, the gate drive voltage must be supplied externally. (See V
GG
and VGG DIS sections
for details.)
V
GG
The V
GG
pin is the gate drive voltage for the high current gate driver stages. For V
IN
≥ 4.75V, the internal V
GG
generator can be used. For V
IN
< 4.75 V, this pin should be driven from an external bias supply. When using the
internal regulator, the VGG_DIS pin should be tied low. When using an external V
GG
, VGG_DIS must be tied to
V
GG
. Current is drawn from the V
GG
supply in fast, high-current pulses. A 4.7μF ceramic capacitor (10V
minimum) should be connected from the V
GG
pin to the PGND pin as close as possible to the package. Whether
internally or externally supplied, the voltage on the V
GG
pin is monitored by the ULVO circuitry. The voltage must
be higher than the UVLO threshold before power conversion can occur. The average current drawn from the V
GG
supply is dependant on the switching frequency, the absolute value of V
GG
and the total gate charge of the power
FETs inside the device.
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