Datasheet

P + 2.2 nF 12
2
300 kHz + 0.095 W
I +
P
V
+
0.095 W
12 V
+ 7.9 mA
UCD7201
www.ti.com SLUS645E –FEBRUARY 2005–REVISED NOVEMBER 2009
This power is dissipated in the resistive elements of the circuit. Thus, with no external resistor between the driver
and gate, this power is dissipated inside the driver. Half of the total power is dissipated when the capacitor is
charged, and the other half is dissipated when the capacitor is discharged.
With V
DD
= 12 V, C
LOAD
= 2.2 nF, and f = 300 kHz, the power loss can be calculated as:
(3)
With a 12-V supply, this would equate to a current of:
(4)
Operational Waveforms
Figure 24 shows the circuit performance achievable with the output driving a 10-nF load at 12-V V
DD
. The input
pulsewidth (not shown) is set to 200 ns to show both transitions in the output waveform. Note the linear rising
and falling edges of the switching waveforms. This is due to the constant output current characteristic of
TrueDrive™ stage as opposed to the resistive output impedance of traditional MOSFET-based gate drivers.
Thermal Information
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal
characteristics of the device package. In order for a power driver to be useful over a particular temperature range
the package must allow for the efficient removal of the heat produced while keeping the junction temperature
within rated limits. The UCD7K family of drivers is available in PowerPAD™ TSSOP and QFN/DFN packages to
cover a range of application requirements. Both have an exposed pad to enhance thermal conductivity from the
semiconductor junction.
As illustrated in Reference [2], the PowerPAD™ packages offer a leadframe die pad that is exposed at the base
of the package. This pad is soldered to the copper on the PC board (PCB) directly underneath the device
package, reducing the T
JC
down to 2.07°C/W. The PC board must be designed with thermal lands and thermal
vias to complete the heat removal subsystem, as summarized in Reference [3].
Note that the PowerPAD™ is not directly connected to any leads of the package. However, it is electrically and
thermally connected to the substrate which is the ground of the device. The PowerPad™ should be connected to
the quiet ground of the circuit.
Circuit Layout Recommendations
In a power driver operating at high frequency, it is critical to minimize stray inductance to minimize
overshoot/undershoots and ringing. The low output impedance of these drivers produces waveforms with high
di/dt. This tends to induce ringing in the parasitic inductances. It is advantageous to connect the driver device
close to the MOSFETs. It is recommended that the PGND and the AGND pins be connected to the PowerPad™
of the package with a thin trace. It is critical to ensure that the voltage potential between these two pins does not
exceed 0.3 V. The use of schottky diodes on the outputs to PGND and PVDD is recommended when driving gate
transformers.
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