Datasheet

UCD7201
www.ti.com SLUS645E –FEBRUARY 2005–REVISED NOVEMBER 2009
APPLICATION INFORMATION
The UCD7201 is member of the UCD7K family of digital compatible drivers targeting applications utilizing digital
control techniques or applications that require local fast peak current limit protection.
Supply
The UCD7K devices accept a supply range of 4.5 V to 15 V. The device has an internal precision linear regulator
that produces the 3V3 output from this VDD input. A separate pin, PVDD, not connected internally to the VDD
supply rail provides power for the output drivers. In all applications the same bus voltage supplies the two pins. It
is recommended that a low value of resistance be placed between the two pins so that the local capacitance on
each pin forms low pass filters to attenuate any switching noise that may be on the bus.
Although quiescent VDD current is low, total supply current depends on the gate drive output current required for
capacitive load and switching frequency. Total VDD current is the sum of quiescent VDD current and the average
OUT current. Knowing the operating frequency and the MOSFET gate charge (Q
G
), average OUT current can be
calculated from:
I
OUT
= Q
G
x f, where f is frequency.
For the best high-speed circuit performance, VDD bypass capacitors are recommended to prevent noise
problems. A 4.7-μF ceramic capacitor should be located closest to the VDD and the AGND connection. In
addition, a larger capacitor with relatively low ESR should be connected to the PVDD and PGND pin, to help
deliver the high current peaks to the load. The capacitors should present a low impedance characteristic for the
expected current levels in the driver application. The use of surface mount components for all bypass capacitors
is highly recommended.
Reference / External Bias Supply
All devices in the UCD7K family are capable of supplying a regulated 3.3-V rail to power various types of external
loads such as a microcontroller or an ASIC. The onboard linear voltage regulator is capable of sourcing up to 10
mA of current. For normal operation, place 0.22-μF of ceramic capacitance between the 3V3 pin to the AGND
pin.
Input Pin
The input pins are high impedance digital inputs capable of accepting 3.3-V logic level signals up to 2 MHz.
There is an internal Schmitt Trigger comparator which isolates the internal circuitry from any external noise.
If limiting the rise or fall times to the power device is desired then an external resistance may be added between
the output of the driver and the load device, which is generally the gate of a power MOSFET.
Current Sensing and Protection
A very fast current limit comparator connected to the CS pin is used to protect the power stage by implementing
cycle-by-cycle current limiting.
The current limit threshold may be set to any value between 0.25 V and 1.0 V by applying the desired threshold
voltage to the current limit (ILIM) pin. If the ILIM pin is left floating, the internal current limit threshold will be 0.5
volts. When the CS level is greater than the I
LIM
voltage minus 25 mV, the output of the driver is forced low and
the current limit flag (CLF) is set high. The CLF signal is latched high until the device receives the next rising
edge on either of the IN pins.
When the CS voltage is below I
LIM
, the driver output follows the PWM input. The CLF digital output flag can be
monitored by the host controller to determine when a current limit event occurs and to then apply the appropriate
algorithm to obtain the desired current limit profile (i.e. straight time, fold back, hickup or latch-off).
A benefit of this local protection feature is that the UCD7K devices can protect the power stage if the software
code in the digital controller becomes corrupted. If the controller’s PWM output stays high, the local current
sense circuit turns off the driver output when an over-current event occurs. The system would then likely go into
retry mode because most DSP and microcontrollers have on-board watchdog, brown-out, and other supervisory
peripherals to restart the device in the event that it is not operating properly. But these peripherals typically do
not react fast enough to save the power stage. The UCD7K’s local current limit comparator provides the required
fast protection for the power stage.
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Product Folder Link(s): UCD7201