Datasheet
UCD7201
SLUS645E –FEBRUARY 2005–REVISED NOVEMBER 2009
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TERMINAL FUNCTIONS
UCD7201
PIN
I/O FUNCTION
HTSSOP QFN-16
NAME
-14 PIN # PIN #
1 - NC - No Connection
Regulated 3.3-V rail. The onboard linear voltage regulator is capable of sourcing up to 10 mA
2 1 3V3 O
of current. Place 0.22 μF of ceramic capacitance from this pin to ground.
The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up
3 2 IN1 I to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry
from any external noise.
4 3 AGND - Analog ground return.
The IN pin is a high impedance digital input capable of accepting 3.3-V logic level signals up
5 4 IN2 I to 2 MHz. There is an internal Schmitt trigger comparator which isolates the internal circuitry
from any external noise.
Current limit flag. When the CS level is greater than the ILIM voltage minus 25 mV, the output
6 5 CLF O of the driver is forced low and the current limit flag (CLF) is set high. The CLF signal is
latched high until the device receives the next rising edge on the IN pin.
Current limit threshold set pin. The current limit threshold can be set to any value between
7 6 ILIM I
0.25 V and 1.0 V. The default value while open is 0.5 V.
Current sense pin. Fast current limit comparator connected to the CS pin is used to protect
8 7 CS I
the power stage by implementing cycle-by-cycle current limiting.
Power ground return. The pin should be connected very closely to the source of the power
9 8, 9 PGND -
MOSFET.
10 10 OUT2 O The high-current TrueDrive™ driver output.
11 11 OUT1 O The high-current TrueDrive™ driver output.
Supply pin provides power for the output drivers. It is not connected internally to the VDD
12 12 PVDD I
supply rail. The bypass capacitor for this pin should be returned to PGND.
Supply input pin to power the driver. The UCD7K devices accept an input range of 4.5 V to 15
13 13 VDD I
V. Bypass the pin with at least 4.7 μF of capacitance, returned to AGND.
14, 15, No Connection.
14 NC -
16
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