Datasheet

UCD7201
SLUS645E –FEBRUARY 2005–REVISED NOVEMBER 2009 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
V
DD
= 12 V, 4.7-μF capacitor from V
DD
to GND, 0.22μF from 3V3 to AGND, T
A
= T
J
= -40°C to 105°C, (unless otherwise
noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CURRENT LIMIT (ILIM)
ILIM internal current limit threshold I
LIM
= OPEN 0.51 0.55 0.58
ILIM maximum current limit threshold I
LIM
= 3.3 V 1.05 1.10 1.15
ILIM current limit threshold I
LIM
= 0.75 V 0.700 0.725 0.750
V
ILIM minimum current limit threshold I
LIM
= 0.25 V 0.21 0.23 0.25
CLF output high level CS > I
LIM
, I
LOAD
= -7 mA 2.64 - -
CLF output low level CS ≤ I
LIM
, I
LOAD
= 7 mA - - 0.66
Propagation delay from IN to CLF IN rising to CLF falling after a current limit event - 10 20 ns
CURRENT SENSE COMPARATOR
Bias voltage Includes CS comp offset 5 25 50 mV
Input bias current - –1 - μA
Propagation delay from CS to OUTx I
LIM
= 0.5 V, measured on OUTx, CS = threshold + 60 mV - 25 40
ns
Propagation delay from CS to CLF I
LIM
= 0.5 V, measured on CLF, CS = threshold + 60 mV - 25 50
CURRENT SENSE DISCHARGE TRANSISTOR
Discharge resistance IN = low, resistance from CS to AGND 10 35 75 Ω
OUTPUT DRIVERS
Source current VDD = 12 V, IN = high, OUTx = 5 V 4
Sink current VDD = 12 V, IN = low, OUTx = 5 V 4
A
Source current VDD = 4.75 V, IN = high, OUTx = 0 2
Sink current VDD = 4.75 V, IN = low, OUTx = 4.75 V 3
Rise time, t
R
C
LOAD
= 2.2 nF, VDD = 12 V 10 20
ns
Fall time, t
F
C
LOAD
= 2.2 nF, VDD = 12 V 10 15
Output with VDD < UVLO VDD =1.0 V, I
SINK
= 10 mA 0.8 1.2 V
Propagation delay from IN to OUT1,
C
LOAD
= 2.2 nF, VDD = 12 V, CLK rising 20 35
t
D1
ns
Propagation delay from IN to OUT2,
C
LOAD
= 2.2 nF, VDD = 12 V, CLK falling 20 35
t
D2
4 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated
Product Folder Link(s): UCD7201