Datasheet

Front End 2
Analog
Comparators
Power and
1.8 V Voltage
Regulator
AD07
AD06
AD04
V33DIO /RESET
SCI_RX0
SCI_TX0
PMBUS_CLK
PMBUS_DATA
AGND
V33D
BP18
FAULT3
FAULT2
TCAP
TMS
TDI
TDO
TCK
EXT_INT
FAULT1
FAULT0
P W M 1
P
W M 0
S C I _ R X 1
S C I _ T X 1
P M B U S _ C T R L
P M B U S _ A L E R T
S Y N C
D G N D
D P W M 3 B
D P W M 3 A
D P W M 2 B
D P W M 2 A
D P W M 1 B
D P W M 1 A
D P W M 0 B
D P W M 0 A
E A P 0
E A N 0
E A P 1
E A N 1
V 3 3 A
A D 0 0
A D 0 1
A D 0 2
A D 1 3
PID Based
Filter 0
DPWM0
DPWM1
DPWM2
DPWM3
PID Based
Filter 1
PID Based
Filter 2
A D C _ E X T _ T R I G
ADC12
ADC12 Control
Sequencing, Averaging,
Digital Compare, Dual
Sample and hold
A D [ 1 3 : 0 ]
A
B
C
D
E
F
G
Current Share
Analog, Average, Master/Slave
AD03
A D 0 2
A D 1 3
AGND
PMBus
Timers
4 – 16 bit (PWM)
1 – 24 bit
UART0
UART1
GPIO
Control
JTAG
Loop MUX
ARM7TDMI-S
32 bit, 31.25 MHz
Memory
PFLASH 32 kB
DFLASH 2 kB
RAM 4 kB
ROM 4 kB
Power On Reset
Brown Out Detection
Oscillator
Internal Temperature
Sensor
Advanced Power Control
Mode Switching, Burst Mode, IDE,
Synchronous Rectification soft on & off
Front End 1
Constant Power Constant
Current
Input Voltage Feed Forward
Front End Averaging
Digital Comparators
Fault MUX &
Control
Cycle by Cycle
Current Limit
Digital
Comparators
DAC0
EADC
X
AFE
Value
Dither
Σ
CPCC
Filter x
Ramp
SAR/Prebias
Abs()
Avg()
2
AFE
2
3-AFE
Peak Current Mode
Control Comparator
A
0
E A P 2
E A N 2
Front End 0
UCD3138
www.ti.com SLUSAP2F –MARCH 2012–REVISED NOVEMBER 2013
2.4 Functional Block Diagram
NOTE
Front-end 2 Recommended for Peak Current Mode Control
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