Datasheet

Digital Comparator 0
Control
Digital Comparator 1
Control
Digital Comparator 2
Control
Digital Comparator 3
Control
Front End
Control 0
Front End
Control 1
Front End
Control 2
Analog
Comparator 0
Analog Comparator 0
Control
Analog
Comparator 1
Analog Comparator 1
Control
Analog
Comparator 2
Analog Comparator 2
Control
Analog
Comparator 3
Analog Comparator 3
Control
Analog
Comparator 4
Analog Comparator 4
Control
Analog
Comparator 5
Analog Comparator 5
Control
Analog
Comparator 6
Analog Comparator 6
Control
External GPIO
Detection
fault[2:0]
DPWM 0 DPWM 1 DPWM 2 DPWM 3
DPWM 0
Fault Control
DPWM 1
Fault Control
DPWM 2
Fault Control
DPWM 3
Fault Control
Analog Comparator
Automated Ramp
DCM Detection
HFO/LFO
Fail Detect
UCD3138
www.ti.com SLUSAP2F –MARCH 2012–REVISED NOVEMBER 2013
Figure 4-5. Fault Mux Block Diagram
4.15 Communication Ports
4.15.1 SCI (UART) Serial Communication Interface
A maximum of two independent Serial Communication Interface (SCI) or Universal Asynchronous
Receiver/Transmitter pre-scaler (UART) interfaces are included within the device for asynchronous start-
stop serial data communication (see the pin out sections for details) Each interface has a 24 bit for
supporting programmable baud rates and has programmable data word and stop bit options. Half or full
duplex operation is configurable through register bits. A loop back feature can also be setup for firmware
verification. Both SCI-TX and SCI-RX pin sets can be used as GPIO pins when the peripheral is not being
used.
4.15.2 PMBUS
The PMBus Interface supports independent master and slave modes controlled directly by firmware
through a processor bus interface. Individual control and status registers enable firmware to send or
receive I2C, SMBus or PMBus messages in any of the accepted protocols, in accordance with the I
2
C
Specification, SMBus Specification (Version 2.0) and the PMBUS Power System Management Protocol
Specification.
The PMBus interface is controlled through a processor bus interface, utilizing a 32-bit data bus and 6-bit
address bus. The PMBus interface is connected to the expansion bus, which features 4 byte write
enables, a peripheral select dedicated for the PMBus interface, separated 32-bit data buses for reading
and writing of data and active-low write and output enable control signals. In addition, the PMBus Interface
connects directly to the I
2
C/SMBus/PMBus Clock, Data, Alert, and Control signals.
Example: PMBus Address Decode via ADC12 Reading
The user can allocate 2 pins of the 12-bit ADC input channels, AD_00 and AD_01, for PMBus address
decoding. At power-up the device applies I
BIAS
to each address detect pin and the voltage on that pin is
captured by the internal 12-bit ADC.
Where bin(V
AD0x
) is the address bin for one of 12 address as shown in Figure 4-6.
Copyright © 2012–2013, Texas Instruments Incorporated Functional Overview 51
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