Datasheet

UCD3138
www.ti.com SLUSAP2F –MARCH 2012–REVISED NOVEMBER 2013
The Sample Trigger signals are used to trigger the Front End to sample input signals. The Blanking
signals are used to blank fault measurements during noisy events, such as FET turn on and turn off.
Additional DPWM modes are described below.
4.4.1.4 High Resolution DPWM
Unlike conventional PWM controllers where the frequency of the clock dictates the maximum resolution of
PWM edges, the UCD3138 DPWM can generate waveforms with resolutions as small as 250 ps. This is
16 times the resolution of the clock driving the DPWM module.
This is achieved by providing the DPWM mechanism with 16 phase shifted clock signals of 250 MHz
each. The high resolution section of DPWM can be enabled or disabled, also the resolution can be defined
in several steps between 4ns to 250ps. This is done by setting the values of PWM_HR_MULTI_OUT_EN ,
HIRES_SCALE and ALL_PHASE_CLK_ENA inside the DPWM Control Register 1. See the Power
Peripherals programmer’s manual for details.
4.4.1.5 Over Sampling
The DPWM module has the capability to trigger an over sampling event by initiating the EADC to sample
the error voltage. The default “00” configuration has the DPWM trigger the EADC once based on the
sample trigger register value. The over sampling register has the ability to trigger the sampling 2, 4 or 8
times per PWM period. Thus the time the over sample happens is at the divide by 2, 4, or 8 time set in the
sampling register. The “01” setting triggers 2X over sampling, the “10” setting triggers 4X over sampling,
and the “11” triggers over sampling at 8X.
4.4.1.6 DPWM Interrupt Generation
The DPWM has the capability to generate a CPU interrupt based on the PWM frequency programmed in
the period register. The interrupt can be scaled by a divider ratio of up to 255 for developing a slower
interrupt service execution loop. This interrupt can be fed to the ADC circuitry for providing an ADC12
trigger for sequence synchronization. Table 4-2 outlines the divide ratios that can be programmed.
4.4.1.7 DPWM Interrupt Scaling/Range
Table 4-2. DPWM Interrupt Divide Ratio
Switching Period
Interrupt Divide Interrupt Divide Interrupt Divide Number of 32 MHz
Frames (assume 1MHz
Setting Count Count (hex) Processor Cycles
loop)
1 0 00 1 32
2 1 01 2 64
3 3 03 4 128
4 7 07 8 256
5 15 0F 16 512
6 31 1F 32 1024
7 47 2F 48 1536
8 63 3F 64 2048
9 79 4F 80 2560
10 95 5F 96 3072
11 127 7F 128 4096
12 159 9F 160 5120
13 191 BF 192 6144
14 223 DF 224 7168
15 255 FF 256 8192
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