Datasheet

UCD3138
www.ti.com SLUSAP2F –MARCH 2012–REVISED NOVEMBER 2013
The output of the filter feeds the high resolution DPWM module. The DPWM module produces the pulse
width modulated outputs for the power stage switches. The compensator calculates the necessary duty
ratio as a 24-bit number in Q23 fixed point format (23 bit integer with 1 sign bit). This represents a value
within the range 0.0 to 1.0. This duty ratio value is used to generate the corresponding DPWM output ON
time. The resolution of the DPWM ON time is 250 psec.
Each DPWM module can be synchronized to another module or to an external sync signal. An input
SYNC signal causes a DPWM ramp timer to reset. The SYNC signal outputs—from each of the four
DPWM modules—occur when the ramp timer crosses a programmed threshold. In this way the phase of
the DPWM outputs for multiple power stages can be tightly controlled.
The DPWM logic is probably the most complex of the Digital Peripherals. It takes the output of the
compensator and converts it into the correct DPWM output for several power supply topologies. It
provides for programmable dead times and cycle adjustments for current balancing between phases. It
controls the triggering of the EADC. It can synchronize to other DPWMs or to external sources. It can
provide synchronization information to other DPWMs or to external recipients. In addition, it interfaces to
several fault handling circuits. Some of the control for these fault handling circuits is in the DPWM
registers. Fault handling is covered in the Fault Mux section.
Each DPWM module supports the following features:
• Dedicated 14 bit time-base with period and frequency control
• Shadow period register for end of period updates.
• Quad-event control registers (A and B, rising and falling) (Events 1-4)
– Used for on/off DPWM duty ratio updates.
• Phase control relative to other DPWM modules
• Sample trigger placement for output voltage sensing at any point during the DPWM cycle.
• Support for 2 independent edge placement DPWM outputs (same frequency or period setting)
• Dead-time between DPWM A and B outputs
• High Resolution capabilities – 250 ps
• Pulse cycle adjustment of up to ±8.192 µs ( 32768 × 250 ps)
• Active high/ active low output polarity selection
• Provides events to trigger both CPU interrupts and start of ADC12 conversions.
4.4.1.3 DPWM Events
Each DPWM can control the following timing events:
1. Sample Trigger Count–This register defines where the error voltage is sampled by the EADC in
relationship to the DPWM period. The programmed value set in the register should be one fourth of the
value calculated based on the DPWM clock. As the DCLK (DCLK = 62.5 MHz max) controlling the
circuitry runs at one fourth of the DPWM clock (PCLK = 250MHz max). When this sample trigger count
is equal to the DPWM Counter, it initiates a front end calculation by triggering the EADC, resulting in a
CLA calculation, and a DPWM update. Over-sampling can be set for 2, 4 or 8 times the sampling rate.
2. Phase Trigger Count–count offset for slaving another DPWM (Multi-Phase/Interleaved operation).
3. Period–low resolution switching period count. (count of PCLK cycles)
4. Event 1–count offset for rising DPWM A event. (PCLK cycles)
5. Event 2–DPWM count for falling DPWM A event that sets the duty ratio. Last 4 bits of the register are
for high resolution control. Upper 14 bits are the number of PCLK cycle counts.
6. Event 3–DPWM count for rising DPWM B event. Last 4 bits of the register are for high resolution
control. Upper 14 bits are the number of PCLK cycle counts.
7. Event 4–DPWM count for falling DPWM B event. Last 4 bits of the register are for high resolution
control. Upper 14 bits are the number of PCLK cycle counts.
8. Cycle Adjust–Constant offset for Event 2 and Event 4 adjustments.
Copyright © 2012–2013, Texas Instruments Incorporated Functional Overview 29
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