Datasheet

E A P 0
E A N 0
DAC0
EADC
4 bit dithering gives 14 bits of effective resolution
97.65625 µV/LSB effective resolution
X
6 bit ADC
8 mV/LSB
Signed 9 bit result
(error) 1 mV /LSB
AFE_GAIN
10 bit DAC
1.5625 mV/LSB
Value
Dither
S
CPCC
Filter x
Ramp
SAR/Prebias
Absolute Value
Calculation
Averaging
10 bit result
1.5625 mV/LSB
2
3-AFE_GAIN
Peak Current Mode
Comparator
Peak Current
Detected
A
0
2
AFE_GAIN
I
OFFSET
R
EA
EAP
EAN
AGND
AGND
I
OFFSET
R
EA
Front End Differential
Amplifier
UCD3138
SLUSAP2F –MARCH 2012 –REVISED NOVEMBER 2013 www.ti.com
Figure 4-1. Input Stage of EADC Module
Figure 4-2. Front End Module
(Front End 2 Recommended for Peak Current Mode Control)
4.4.1.2 DPWM Module
The DPWM module represents one complete DPWM channel with 2 independent outputs, A and B.
Multiple DPWM modules within the UCD3138 system can be configured to support all key power
topologies. DPWM modules can be used as independent DPWM outputs, each controlling one power
supply output voltage rail. It can also be used as a synchronized DPWM—with user selectable phase shift
between the DPWM channels to control power supply outputs with multiphase or interleaved DPWM
configurations.
28 Functional Overview Copyright © 2012–2013, Texas Instruments Incorporated
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