Datasheet

UCD3138
SLUSAP2F –MARCH 2012 –REVISED NOVEMBER 2013 www.ti.com
4.3.4 Central Interrupt Module (CIM)
The CIM accepts 32 interrupt requests for meeting firmware timing requirements. The ARM processor
supports two interrupt levels: FIQ and IRQ. FIQ is the highest priority interrupt. The CIM provides
hardware expansion of interrupts by use of FIQ/IRQ vector registers for providing the offset index in a
vector table. This numerical index value indicates the highest precedence channel with a pending interrupt
and is used to locate the interrupt vector address from the interrupt vector table. Interrupt channel 0 has
the lowest precedence and interrupt channel 31 has the highest precedence. To remove the interrupt
request, the firmware should clear the request as the first action in the interrupt service routine. The
request channels are maskable, allowing individual channels to be selectively disabled or enabled.
Table 4-1. Interrupt Priority Table
MODULE COMPONENT OR
NAME DESCRIPTION PRIORITY
REGISTER
BRN_OUT_INT Brownout Brownout interrupt 0 (Lowest)
EXT_INT External Interrupts Interrupt on external input pin 1
WDRST_INT Watchdog Control Interrupt from watchdog exceeded (reset) 2
Wakeup interrupt when watchdog equals half of set
WDWAKE_INT Watchdog Control 3
watch time
SCI_ERR_INT UART or SCI Control UART or SCI error Interrupt. Frame, parity or overrun 4
SCI_RX_0_INT UART or SCI Control UART0 RX buffer has a byte 5
SCI_TX_0_INT UART or SCI Control UART0 TX buffer empty 6
SCI_RX_1_INT UART or SCI Control UART1 RX buffer has a byte 7
SCI_TX_1_INT UART or SCI Control UART1 TX buffer empty 8
PMBUS_INT PMBus related interrupt 9
DIG_COMP_INT 12-bit ADC Control Digital comparator interrupt 10
“Prebias complete”, “Ramp Delay Complete”, “Ramp
FE0_INT Front End 0 Complete”, “Load Step Detected”, 11
“Over-Voltage Detected”, “EADC saturated ”
“Prebias complete”, “Ramp Delay Complete”, “Ramp
FE1_INT Front End 1 Complete”, “Load Step Detected”, 12
“Over-Voltage Detected”, “EADC saturated ”
“Prebias complete”, “Ramp Delay Complete”, “Ramp
FE2_INT Front End 2 Complete”, “Load Step Detected”, 13
“Over-Voltage Detected”, “EADC saturated ”
PWM3_INT 16-bit Timer PWM 3 16-bit Timer PWM3 counter overflow or compare interrupt 14
16-bit Timer PWM2 counter Overflow or compare
PWM2_INT 16-bit Timer PWM 2 15
interrupt
PWM1_INT 16-bit Timer PWM 1 16-bit Timer PWM1 counter overflow or compare interrupt 16
PWM0_INT 16-bit timer PWM 0 16-bit Timer PWM1 counter overflow or compare interrupt 17
OVF24_INT 24-bit Timer Control 24-bit Timer counter overflow interrupt 18
CAPTURE_1_INT 24-bit Timer Control 24-bit Timer capture 1 interrupt 19
COMP_1_INT 24-bit Timer Control 24-bit Timer compare 1 interrupt 20
CAPTURE_0_INT 24-bit Timer Control 24-bit Timer capture 0 interrupt 21
COMP_0_INT 24-bit Timer Control 24-bit Timer compare 0 interrupt 22
Mode switched in CPCC module Flag needs to be read
CPCC_INT Constant Power Constant Current 23
for details
ADC_CONV_INT 12-bit ADC Control ADC end of conversion interrupt 24
Analog comparator interrupts, Over-Voltage detection,
FAULT_INT Fault Mux Interrupt Under-Voltage detection, 25
LLM load step detection
26 Functional Overview Copyright © 2012–2013, Texas Instruments Incorporated
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