Datasheet

UCD3138

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SLUSAP2F –MARCH 2012–REVISED NOVEMBER 2013

The Boot ROM is entered automatically on device reset. It initializes the device and then performs

checksums on the Program FLASH. If the first 2 kB of program FLASH has a valid checksum, the

program jumps to location 0 in the Program FLASH. This permits the use of a customer boot program. If

the first checksum fails, it performs a checksum on the complete 32 kB of program flash. If this is valid, it

also jumps to location 0 in the program flash. This permits full automated program memory checking,

when there is no need for a custom boot program.

If neither checksum is valid, the Boot ROM stays in control, and accepts commands via the PMBus

interface

These functions can be used to read and write to all memory locations in the UCD3138. Typically they are

used to download a program to Program Flash, and to command its execution

4.2.3 Customer Boot Program

As described above, it is possible to generate a user boot program using 2 kB or more of the Program

Flash. This can support things which the Boot ROM does not support, including:

• Program download via UART – useful especially for applications where the UCD3138 is isolated from

the host (e.g., PFC)

• Encrypted download – useful for code security in field updates.

4.2.4 Flash Management

The UCD3138 offers a variety of features providing for easy prototyping and easy flash programming. At

the same time, high levels of security are possible for production code, even with field updates. Standard

firmware will be provided for storing multiple copies of system parameters in data flash. This is minimizes

the risk of losing information if programming is interrupted.

4.3 System Module

The System Module contains the interface logic and configuration registers to control and configure all the

memory, peripherals and interrupt mechanisms. The blocks inside the system module are the address

decoder, memory management controller, system management unit, central interrupt unit, and clock

control unit.

4.3.1 Address Decoder (DEC)

The Address Decoder generates the memory selects for the FLASH, ROM and RAM arrays. The memory

map addresses are selectable through configurable register settings. These memory selects can be

configured from 1 kB to 16 MB. Power on reset uses the default addresses in the memory map for ROM

execution, which is then configured by the ROM code to the application setup. During access to the DEC

registers, a wait state is asserted to the CPU. DEC registers are only writable in the ARM privilege mode

for user mode protection.

4.3.2 Memory Management Controller (MMC)

The MMC manages the interface to the peripherals by controlling the interface bus for extending the read

and write accesses to each peripheral. The unit generates eight peripheral select lines with 1 kB of

address space decoding.

4.3.3 System Management (SYS)

The SYS unit contains the software access protection by configuring user privilege levels to memory or

peripherals modules. It contains the ability to generate fault or reset conditions on decoding of illegal

address or access conditions. A clock control setup for the processor clock (MCLK) speed, is also

available.

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