Datasheet

UCD3138
www.ti.com SLUSAP2F –MARCH 2012–REVISED NOVEMBER 2013
ELECTRICAL CHARACTERISTICS (continued)
V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, T
J
= –40°C to 125°C (unless otherwise noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
ADC12 INL integral nonlinearity
(1)
+/-2.5 LSB
ADC12 DNL differential nonlinearity
(1)
–0.7/+2.5 LSB
ADC_SAMPLINGSEL = 6 for all ADC12
data, 25 °C to 125 °C
ADC Zero Scale Error –7 7 mV
ADC Full Scale Error –35 35 mV
Input bias 2.5 V applied to pin 400 nA
Input leakage resistance
(1)
ADC_SAMPLINGSEL= 6 or 0 1 MΩ
Input Capacitance
(1)
10 pF
ADC single sample conversion time
(1)
ADC_SAMPLINGSEL= 6 or 0 3.9 μs
DIGITAL INPUTS/OUTPUTS
(2)(3)
DGND
V
OL
Low-level output voltage
(4)
I
OH
= 4 mA, V33DIO = 3 V V
+ 0.25
V33DIO
V
OH
High-level output voltage
(4)
I
OH
= –4 mA, V33DIO = 3 V V
– 0.6
V
IH
High-level input voltage V33DIO = 3 V 2.1 V
V
IL
Low-level input voltage V33DIO = 3 V 1.1 V
I
OH
Output sinking current 4 mA
I
OL
Output sourcing current –4 mA
SYSTEM PERFORMANCE
Total time is: TWD x
TWD Watchdog time out range 14.6 17 20.5 ms
(WDCTRL.PERIOD+1)
Time to disable DPWM output based on
High level on FAULT pin 70 ns
active FAULT pin signal
Processor master clock (MCLK) 31.25 MHz
t
Delay
Digital compensator delay
(5)
(1 clock = 32ns) 6 clocks
t
(reset)
Pulse width needed at reset
(6)
10 µs
Retention period of flash content (data
T
J
= 25°C 100 years
retention and program)
Program time to erase one page or block in
20 ms
data flash or program flash
Program time to write one word in data
20 µs
flash or program flash
f
(PCLK)
Internal oscillator frequency 240 250 260 MHz
Sync-in/sync-out pulse width Sync pin 256 ns
Flash Read 1 MCLKs
Flash Write 20 μs
Current share current source (See
I
SHARE
238 259 μA
Figure 4-9)
R
SHARE
Current share resistor (See Figure 4-9) 9.75 10.3 kΩ
POWER ON RESET AND BROWN OUT (V33D pin, See Figure 3-3)
VGH Voltage good High 2.7 V
VGL Voltage good Low 2.5 V
V
res
Voltage at which IReset signal is valid 0.8 V
Time delay after Power is good or
T
POR
1 ms
RESET* relinquished
(2) DPWM outputs are low after reset. Other GPIO pins are configured as inputs after reset.
(3) On the 40 pin package V33DIO is connected to V33D internally.
(4) The maximum total current, IOHmax and IOLmax for all outputs combined, should not exceed 12 mA to hold the maximum voltage drop
specified. Maximum sink current per pin = –6 mA at V
OL
; maximum source current per pin = 6 mA at V
OH
.
(5) Time from close of error ADC sample window to time when digitally calculated control effort (duty cycle) is available. This delay, which
has no variation associated with it, must be accounted for when calculating the system dynamic response.
(6) As designed and characterized. Not 100% tested in production.
Copyright © 2012–2013, Texas Instruments Incorporated Electrical Specifications 17
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