UCD3138 Highly Integrated Digital Controller for Isolated Power Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 Contents 1 Introduction 1.1 1.2 2 Overview 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 4.3 4.4 4.5 4.6 4.7 4.8 ..................................................................................................... 15 ABSOLUTE MAXIMUM RATINGS ...................................................................................... THERMAL INFORMATION ..............................................................................................
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 Triangular Mode ........................................................................................................... Leading Edge Mode ....................................................................................................... Sync FET Ramp and IDE Calculation .................................................................................. Automatic Mode Switching .........................................................
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com List of Figures 3-1 I2C/SMBus/PMBus Timing Diagram ........................................................................................... 20 3-2 Bus Timing in Extended Mode.................................................................................................. 20 3-3 Power On Reset (POR) / Brown Out Reset (BOR) ..........................................................................
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 List of Tables ..................................................................................................................... ..................................................................................................................... 2 I C/SMBus/PMBus Timing Characteristics .................................................................................... Interrupt Priority Table ...........................................
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com Highly Integrated Digital Controller for Isolated Power Check for Samples: UCD3138 1 Introduction 1.
UCD3138 www.ti.com 1.2 • • • SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 Applications Power Supplies and Telecom Rectifiers Power Factor Correction Isolated dc-dc Modules 2 Overview 2.1 Description The UCD3138 is a digital power supply controller from Texas Instruments offering superior levels of integration and performance in a single chip solution. The flexible nature of the UCD3138 makes it suitable for a wide variety of power conversion applications.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 2.2 www.ti.
UCD3138 www.ti.com 2.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 2.
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 Table 2-1. Pin Functions (continued) PIN NAME PRIMARY ASSIGNMENT ALTERNATE ASSIGNMENT NO. 1 NO. 2 NO.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 AD01 AD00 V33A AGND EAP2 EAN1 EAP1 EAN0 EAP0 UCD3138RHA 40 QFN – Pin Assignments AD02 2.
UCD3138 www.ti.com 40 39 38 37 36 35 34 33 32 EAP0 EAN0 EAP1 EAN1 EAP2 AGND V33A AD00 AD01 UCD3138RMH 40 QFN With Corner Anchors – Pin Assignments AD02 2.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 2.9 www.ti.com Pin Functions (UCD3138RHA and UCD3138RMH) Additional pin functionality is specified in the following table. Table 2-2. Pin Functions PIN PRIMARY ASSIGNMENT ALTERNATE ASSIGNMENT NO. 1 NO. 2 NO.
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 3 Electrical Specifications 3.1 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE UNIT MIN MAX V33D V33D to DGND –0.3 3.8 V V33DIO V33DIO to DGND –0.3 3.8 V V33A V33A to AGND –0.3 3.8 V BP18 BP18 to DGND –0.3 2.5 V |DGND – AGND| Ground difference 0.3 V All Pins, excluding AGND (2) Voltage applied to any pin –0.3 3.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 3.4 www.ti.com ELECTRICAL CHARACTERISTICS V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT SUPPLY CURRENT I33A Measured on V33A. The device is powered up but all ADC12 and EADC sampling is disabled 6.3 mA I33DIO All GPIO and communication pins are open 0.
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 ELECTRICAL CHARACTERISTICS (continued) V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted) PARAMETER TEST CONDITION MIN ADC12 INL integral nonlinearity (1) TYP MAX +/-2.5 ADC12 DNL differential nonlinearity (1) ADC_SAMPLINGSEL = 6 for all ADC12 data, 25 °C to 125 °C ADC Zero Scale Error ADC Full Scale Error LSB –0.7/+2.5 –7 –35 UNIT LSB 7 mV 35 mV Input bias 2.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) V33A = V33D = V33DIO = 3.3V; 1μF from BP18 to DGND, TJ = –40°C to 125°C (unless otherwise noted) PARAMETER Brownout TEST CONDITION MIN Internal signal warning of brownout conditions TYP MAX 2.
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 PMBus/SMBus/I2C Timing 3.5 The timing characteristics and timing diagram for the communications interface that supports I2C, SMBus, and PMBus in Slave or Master mode are shown in Table 3-1, Figure 3-1, and Figure 3-2. The numbers in Table 3-1 arµe for 400 kHz operating frequency. However, the device supports all three speeds, standard (100 kHz), fast (400 kHz), and fast mode plus (1 MHz). Table 3-1.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com Figure 3-2. Bus Timing in Extended Mode 3.6 Power On Reset (POR) / Brown Out Reset (BOR) V33D 3.3 V Brown Out VGH VGL Vres t TPOR IReset TPOR t undefined Figure 3-3. Power On Reset (POR) / Brown Out Reset (BOR) 20 VGH – This is the V33D threshold where the internal power is declared good. The UCD3138 comes out of reset when above this threshold. VGL – This is the V33D threshold where the internal power is declared bad.
UCD3138 www.ti.com 3.7 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 Typical Clock Gating Power Savings 6 Power Savings (mA) 5 4.9 4 3 2.57 2 1.2 1 0.8 0.4 0.4 0.2 0.2 0.1 0.1 0 SCI SCI GIO 0 DPWM FE_CTRL PCM ADC12 PMBUS TIMER CPCC FILTER UCD3138 Function G001 Power disable control register provides control bits that can enable or disable arrival of clock to several peripherals such as, PCM, CPCC, digital filters, front ends, DPWMs, UARTs, ADC-12 and more.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 3.8 www.ti.com Typical Temperature Characteristics 1.81 2 1.79 Voltage (V) EADC LSB Size (mV) sp 2.1 1.9 1.8 1.7 1.6 −40 1.77 1.75 Minimum Maximum Typical 1.73 −20 0 20 40 60 Temperature (°C) 80 100 1.71 120 -50 8 2.4 6 ADC12 Error (LSB) Sensor Voltage (V) ADC12 Measurement Temperature Sensor Voltage 2.0 1.8 100 150 C001 Figure 3-5. BP18 Voltage vs Temperature 2.6 2.2 50 Temperature (C) Figure 3-4.
UCD3138 www.ti.com 4 Functional Overview 4.1 ARM Processor SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 The ARM7TDMI-S processor is a synthesizable member of the ARM family of general purpose 32-bit microprocessors. The ARM architecture is based on RISC (Reduced Instruction Set Computer) principles where two instruction sets are available. The 32-bit ARM instruction set and the 16-bit Thumb instruction set.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 4.2.1.2 www.ti.com Memory Map (Normal Operation) Just before the boot ROM program gives control to FLASH program, the ROM configures the memory as follows: Address Size Module 0x0000_0000 – 0x0000_7FFF 32K Program Flash 0x0001_0000 – 0x0001_AFFF 4K Boot ROM 0x0001_8800 – 0x0001_8FFF 2K Data Flash 0x0001_9000 – 0x0001_9FFF 4K Data RAM 4.2.1.
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 The Boot ROM is entered automatically on device reset. It initializes the device and then performs checksums on the Program FLASH. If the first 2 kB of program FLASH has a valid checksum, the program jumps to location 0 in the Program FLASH. This permits the use of a customer boot program. If the first checksum fails, it performs a checksum on the complete 32 kB of program flash.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 4.3.4 www.ti.com Central Interrupt Module (CIM) The CIM accepts 32 interrupt requests for meeting firmware timing requirements. The ARM processor supports two interrupt levels: FIQ and IRQ. FIQ is the highest priority interrupt. The CIM provides hardware expansion of interrupts by use of FIQ/IRQ vector registers for providing the offset index in a vector table.
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 Table 4-1. Interrupt Priority Table (continued) NAME MODULE COMPONENT OR REGISTER DESCRIPTION DPWM3 DPWM3 Same as DPWM1 26 DPWM2 DPWM2 Same as DPWM1 27 DPWM1 DPWM1 1) Every (1-256) switching cycles 2) Fault Detection 3) Mode switching 28 DPWM0 DPWM0 Same as DPWM1 29 EXT_FAULT_INT External Faults Fault pin interrupt 30 SYS_SSI_INT System Software System software interrupt 4.4 PRIORITY 31 (highest) Peripherals 4.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com EAP Front End Differential Amplifier IOFFSET R EA IOFFSET R EA AGND EAN AGND Figure 4-1. Input Stage of EADC Module AFE_GAIN 2 EAP0 3-AFE_GAIN 6 bit ADC 8 mV/LSB EAN0 2 AFE_GAIN EADC X Signed 9 bit result (error) 1 mV /LSB Averaging SAR/Prebias Ramp A0 Filter x DAC0 10 bit DAC 1.5625 mV/LSB CPCC S Value Dither 4 bit dithering gives 14 bits of effective resolution 97.
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 The output of the filter feeds the high resolution DPWM module. The DPWM module produces the pulse width modulated outputs for the power stage switches. The compensator calculates the necessary duty ratio as a 24-bit number in Q23 fixed point format (23 bit integer with 1 sign bit). This represents a value within the range 0.0 to 1.0. This duty ratio value is used to generate the corresponding DPWM output ON time.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com Basic comparisons between the programmed registers and the DPWM counter can create the desired edge placements in the DPWM. High resolution edge capability is available on Events 2, 3 and 4.
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 The Sample Trigger signals are used to trigger the Front End to sample input signals. The Blanking signals are used to blank fault measurements during noisy events, such as FET turn on and turn off. Additional DPWM modes are described below. 4.4.1.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 4.5 www.ti.com DPWM Modes of Operation The DPWM is a complex logic system which is highly configurable to support several different power supply topologies. The discussion below will focus primarily on waveforms, timing and register settings, rather than on logic design. The DPWM is centered on a period counter, which counts up from 0 to PRD, and then is reset and starts over again.
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UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com Blanking A-Begin and Blanking A-End can be used to blank out noise from the MOSFET turn on at the beginning of the period (DPWMA rising edge). Blanking B could be used at the turn off time of DPWMB. The other edges are dynamic, so blanking is more difficult. Cycle Adjust B has no effect in Normal Mode. 4.6 Phase Shifting In most modes, it is possible to synchronize multiple DPWM modules using the phase shift signal.
UCD3138 www.ti.com 4.7 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 DPWM Multiple Output Mode Multi mode is used for systems where each phase has only one driver signal. It enables each DPWM peripheral to drive two phases with the same pulse width, but with a time offset between the phases, and with different cycle adjusts for each phase.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com Event 2 and Event 4 are not relevant in Multi mode. DPWMB can cross over the period boundary safely, and still have the proper pulse width, so full 100% pulse width operation is possible. DPWMA cannot cross over the period boundary. Since the rising edge on DPWM B is also fixed, Blanking B-Begin and Blanking B-End can be used for blanking this rising edge. And, of course, Cycle Adjust B is usable on DPWM B. 4.
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UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 4.9 www.ti.com Triangular Mode Triangular mode provides a stable phase shift in interleaved PFC and similar topologies. In this case, the PWM pulse is centered in the middle of the period, rather than starting at one end or the other. In Triangular Mode, only DPWM-B is available.
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 4.10 Leading Edge Mode Leading edge mode is very similar to Normal mode, reversed in time. The DPWM A falling edge is fixed, and the rising edge moves to the left, or backwards in time, as the filter output increases. The DPWM B falling edge stays ahead of the DPWMA rising edge by a fixed dead time.
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UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 4.11 Sync FET Ramp and IDE Calculation The UCD3138 has built in logic for controlling MOSFETs for synchronous rectification (Sync FETs). This comes in two forms: • Sync FET ramp • Ideal Diode Emulation (IDE) calculation When starting up a power supply, sometimes there is already a voltage on the output – this is called prebias. It is very difficult to calculate the ideal Sync FET on-time for this case.
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UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 VBUS Q1T ILR(t) Transformer LRES QSR2 LK NS RLRES Q1B ILM(t) LM ISEC (t) Driver DPWM1B Oring Circuitry VOUT NP COUT1 NS RF1 COUT2 AD03 EAP0 VBUS ESR1 ESR2 RF2 QSR1 Rectifier and filter CRES VOUT(t) CF EAN0 AD04 RS Driver DPWM1A CS V CR(t) CRES RS1 RS2 Driver DPWM0B Driver DPWM0A ADC13 EAP1 Figure 4-4.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com 4.12.3 Mechanism for Automatic Mode Switching The UCD3138 allows the customer to enable up to two distinct levels of automatic mode switching. These different modes are used to enhance light load operation, short circuit operation and soft start. Many of the configuration parameters for the DPWM are in DPWM Control Register 1.
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 4.13 DPWMC, Edge Generation, IntraMux The UCD3138 has hardware for generating complex waveforms beyond the simple DPWMA and DPWMB waveforms already discussed – DPWMC, the Edge Generation Module, and the IntraMux. DPWMC is a signal inside the DPWM logic. It goes high at the Blanking A begin time, and low at the Blanking A end time.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com 5 = DPWMB(n+1) 6 = DPWMC(n+1) 7 = DPWMC(n+2) 8 = DPWMC(n+3) and for DPWMB: 0 = DPWMB(n) pass through (default) 1 = Edge-gen output, DPWMB(n) 2 = DPWNC(n) 3 = DPWMA(n) (Crossover) 4 = DPWMA(n+1) 5 = DPWMB(n+1) 6 = DPWMC(n+1) 7 = DPWMC(n+2) 8 = DPWMC(n+3) The DPWM number wraps around just like the Edge Gen unit. For DPWM3 the following definitions apply: DPWM(n) DPWM3 DPWM(n+1) DPWM0 DPWM(n+2) DPWM1 DPWM(n+3) DPWM2 4.
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 Here is the first section of the Filter : Limit Comparator Limit 6 Limit 5 …..
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com There is a final section for the filter, which permits its output to be matched to the DPWM: Filter YN S0.23 24 KCompx 14.0 DPWMx Period 14.0 X 38 S14.23 Round to 18 bits, Clamp to Positive 18 14.4 Truncate low 4 bits 14 Filter Period Bits [17:4] 14.0 14 14.0 PERIOD_MULT_SEL Filter Output Clamp High Filter YN (Duty %) S0.23 24 KCompx X 38 S14.23 Round to 18 bits, Clamp to Positive 18 Clamp 14.4 18 Filter Duty 14.4 14.
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 4.14.2 Fault Multiplexer In order to allow a flexible way of mapping several fault triggering sources to all the DPWMs channels, the UCD3138 provides an extensive array of multiplexers that are united under the name Fault Mux module. The Fault Mux Module supports the following types of mapping between all the sources of fault and all different fault response mechanism inside each DPWM module.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com The Fault Mux Module provides a multitude of fault protection functions within the UCD3138 high-speed loop (Front End Control, Filter, DPWM and Loop Mux modules). The Fault Mux Module allows highly configurable fault generation based on digital comparators, high-speed analog comparators and external fault pins.
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UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com Vdd AD00, AD01 pin I BIAS On/Off Control Resistor to set PMBus Address To ADC Mux Figure 4-6. PMBus Address Detection Method 4.15.
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 ADC12 Block ADC12 Registers ADC Averaging S/H ADC Channels 12-bit SAR ADC ADC12 Control Digital Comparators ADC Channel ADC External Trigger (from pin) DPWM Modules Analog Comparators Figure 4-7. ADC12 Control Block Diagram 4.15.4 Timers External to the Digital Power Peripherals there are 3 different types of timers in UCD3138. They are the 24-bit timer, 16-bit timer and the Watchdog timer 4.15.4.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com 4.15.4.2 16-Bit PWM Timers There are four 16 bit counter PWM timers which run off the Interface Clock and can further be divided down by a 8-bit pre-scaler to generate slower PWM time periods. Each timer has two compare registers (Data Registers) for generating the PWM set/unset events. Additionally, each timer has a shadow register (Data Buffer register) which can be used to store CPU updates of compare events while still using the timer.
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 4.19 Global I/O Up to 30 pins in UCD3138 can be configured to serve as a general purpose input or output pin (GPIO). This includes all digital input or output pins except for the RESET pin. The pins that cannot be configured as GPIO pins are the supply pins, ground pins, ADC-12 analog input pins, EADC analog input pins and the RESET pin. There are two ways to configure and use the digital pins as GPIO pins: 1.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com BIT PIN_NAME 11 10 PIN NUMBER UCD3138-64 PIN UCD3138-40 PIN FAULT[2] 42 25 FAULT[1] 36 23 9 FAULT[0] 35, 39 22 8 SYNC 12, 26,37 8, 21 7 DPWM3B 24 18 6 DPWM3A 23 17 5 DPWM2B 22 16 4 DPWM2A 21 15 3 DPWM1B 20 14 2 DPWM1A 19 13 1 DPWM0B 18 12 0 DPWM0A 17 11 4.20 Temperature Sensor Control Temperature sensor control register provides internal temperature sensor enabling and trimming capabilities.
UCD3138 www.ti.com • SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 AD02 has a special ESD protection mechanism that prevents the pin from pulling down the currentshare bus if power is missing from the UCD3138 The simplified current sharing circuitry is shown in the drawing below: 3.3 V ISHARE SW3 Digital 3.3 V 3.3V ESD 3. 2 kΩ 400 Ω 250 Ω AD02 AD13 SW2 ESD SW1 ESD 250 Ω EXT CAP R SHARE ADC12 and CMP ADC12 and CMP Figure 4-9.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 5 www.ti.com IC Grounding and Layout Recommendations • • • Two grounds are recommended: AGND (analog) and DGND (digital). – AGND plane should be on a different layer than DGND, and right under the UCD3138 device. – UCD3138 power pad should be tied to AGND plane by at least 4 vias – AGND plane should be just large enough to connect to all required components.
UCD3138 www.ti.com 6 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 Tools and Documentation The application firmware for UCD3138 is developed on Texas Instruments Code Composer Studio (CCS) integrated development environment (v3.3 recommended). Device programming, real time debug and monitoring/configuration of key device parameters for certain power topologies are all available through Texas Instruments’ FUSION_DIGITAL_POWER_DESIGNER Graphical User Interface (http://www.ti.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com – Miscellaneous Analog Controls (Current Sharing, Brown-Out, Clock-Gating) – PMBUS Interface – General Purpose Input Output (GPIO) – Timer Modules – PMBus – Register Map for all of the above peripherals in UCD3138 3.
UCD3138 www.ti.com 7 References 1. 2. 3. 4. 5. 6. 7. 8. (1) SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 UCD3138 Digital Power Peripherals Programmer’s Manual (Literature Number:SLUU995) UCD3138 Monitoring & Communications Programmer’s Manual (Literature Number:SLUU996) UCD3138 ARM and Digital System Programmer’s Manual (Literature Number:SLUU994) FUSION_DIGITAL_POWER_DESIGNER for Isolated Power Applications (Literature Number: SLUA676 Code Composer Studio Development Tools v3.
UCD3138 SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (March 2012) to Revision A • Added Production Data statement to footnote and removed "Product Preview" banner Changes from Revision A (March 2012) to Revision B • • • • • • • • • • • • • • • • • • • • • • 62 ................................... 6 Page Added Feature bullets ...............................
UCD3138 www.ti.com SLUSAP2F – MARCH 2012 – REVISED NOVEMBER 2013 Changes from Revision C (March 2013) to Revision D • • Page Changed TOPT spec to TJ in Abs Max table with MAX temp of 150°C ....................................................... 15 Added BP18 Voltage vs Temperature graphic ................................................................................. 22 Changes from Revision D (August 2013) to Revision E • • • • • Page Added UCD3138RMH to Feature bullet ............................
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PACKAGE OPTION ADDENDUM www.ti.com 17-Dec-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PACKAGE MATERIALS INFORMATION www.ti.com 13-Dec-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing UCD3138RGCR VQFN RGC 64 UCD3138RGCT VQFN RGC UCD3138RHAR VQFN RHA UCD3138RHAT VQFN UCD3138RMHR UCD3138RMHT SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 64 250 180.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2 40 2500 330.0 16.4 6.3 6.
PACKAGE MATERIALS INFORMATION www.ti.com 13-Dec-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCD3138RGCR VQFN RGC 64 2000 367.0 367.0 38.0 UCD3138RGCT VQFN RGC 64 250 210.0 185.0 35.0 UCD3138RHAR VQFN RHA 40 2500 367.0 367.0 38.0 UCD3138RHAT VQFN RHA 40 250 210.0 185.0 35.0 UCD3138RMHR WQFN RMH 40 2000 367.0 367.0 38.0 UCD3138RMHT WQFN RMH 40 250 210.0 185.0 35.
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