Datasheet

13
UCC1972/3
UCC2972/3
UCC3972/3
The clamp circuit works as follows:
If the voltage at the base of Q4 is equal to the zener (D4)
voltage plus the V
BE
of Q4, the clamp circuit will activate
limiting the voltage in the resonant tank. When the clamp
activates, Q4 is turned on and additional current (set by
R9) is allowed into the feedback capacitor. The peak
clamp voltage is given by:
()
VVV
RR
R
V V PEAK
CLAMP IN BUCK
ZENER BEQ
==
+
·+
–
78
7
4
(16a)
Internal Voltage Clamp Circuit for UCC3973
The over-voltage function is provided internally on the
UCC3973. As shown in the block diagram of the
UCC3972/3, an internal comparitor monitors the instanta
-
neous voltage between VBAT and BUCK. If this voltage
exceeds the over-voltage clamp level (9V nominal), a
current will be sourced from the FB pin to reduce duty cy
-
cle. The source current level increases with over-voltage,
but is typically 100µA at the threshold voltage. As with
the Open Lamp Trip Level, the Voltage Clamp Threshold
is programmed with external resistors R10 and R11.
V
RR
R
V
CLAMP PEAK
=
+
æ
è
ç
ö
ø
÷
·
10 11
10
9
(16b)
A 2k resistor for R10 and a 1k resistor for R11 will result
in a peak (VBAT–V
BUCK
) level of 13.5V. With a 1:67
turns ration transformer, the secondary voltage will be
clamped to 1280 V
RMS
.
The FB pin source current is disabled in the UCC3972.
An optional zener diode D
CLAMP
can be added to either
UCC3972 or UCC3973 designs as shown in Fig. 8. The
zener provides a high speed clamp when power is ini-
tially applied to the circuit and before the voltage clamp
can regulate the feedback loop. D
CLAMP
can be a small
250mW zener since it will only conduct for a few reso-
nant cycles before the voltage clamp takes effect.
D
CLAMP
’s value should be a few volts greater than the
voltage clamp.
Setting the Time Period for Blanking Open Lamp Detec
-
tion
A capacitor on the MODE pin of the UCC3972/3 is used
to blank the open lamp protection circuitry during the ini
-
tial lamp startup. When the IC is initially powered-up, a
20mA current out of the MODE pin charges the capacitor
C
MODE
from ground potential. Since the PWM output is
disabled when the MODE pin is between 0V-1V, open
lamp blanking occurs as C
MODE
is charged from 1V-3V,
giving a soft start period of:
T
C
F
SEC
SS
MODE
=·
10m
(17)
The time required for lamp strike is application depend
-
ent, and a 10mF capacitor allows 1 second in which to
strike the lamp. Fig. 9 shows the voltage at the V
BUCK
node with a 20V input and a 13.5V peak level for the in
-
ternal voltage clamp (UCC3972 requires and external
clamp) under an open lamp fault condition. After the 1
second period, the open lamp detection circuit trips and
the UCC3972/3 shuts down until power is cycled on the
chip.
2
4
V
BUCK
VBAT
T1
C5
Q2
L1
Q1
D
CLAMP
R8
R7
R9
D4
R3
UCC3972 EXTERNAL
VO LTAG E C LAMP
R4D2
FB
LAMP
Q4
2N3906
Figure 8. Optional voltage clamp circuit. For UCC3972. (Not required for UCC3973)
APPLICATION INFORMATION (cont.)
UDG-99161