User’s Guide UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A User’s Guide 1
EVM IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation kit being sold by TI is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not considered by TI to be fit for commercial use.
DYNAMIC WARNINGS AND RESTRICTIONS It is important to operate this EVM within the maximum input voltage ranges specified. Exceeding the specified input range may cause unexpected operation and/or irreversible damage to the EVM. If there are questions concerning the input range, please contact a TI field representative prior to connecting the input power. Applying loads outside of the specified output range may result in unintended operation and/or possible permanent damage to the EVM.
SLUU166A - December 2003 − Revised February 2004 UCC39002 Advanced Load-Share Controller User’s Guide, HPA027A System Power Lisa Dinwoodie ABSTRACT The UCC39002 is an advanced, high-performance load-share controller that provides all the necessary functions to parallel multiple independent power supplies or dc-to-dc modules.
SLUU166A - December 2003 − Revised February 2004 3 Applications This user’s guide will enable the user to select components to successfully parallel power modules that have the following features: D Remote sense D Output voltages greater than 1 V, but less than 15 V D An output stage that sources output current only, allowing for paralleling of converters and ensuring one converter does not sink current from another converter.
SLUU166A - December 2003 − Revised February 2004 The available evaluation boards come pre−populated with the load share controllers, VDD decoupling capacitors, and components for external controller shut down. This circuitry is shown in Figure 1 as U1, C5, Q1, R1, and R4 for the first module, U2, C7, Q2, R2, R5 for the second, and U3, C9, Q3, R3, and R6 for the third.
SLUU166A - December 2003 − Revised February 2004 6 Design Procedure The following is a step-by-step design procedure on how to determine the appropriate components to parallel power modules for load sharing. The user’s guide is stated for the first module and the circuit is repeated for each of the remaining two modules.
SLUU166A - December 2003 − Revised February 2004 GAIN AND PHASE vs FREQUENCY 100 0 Gain − dB 50 −100 0 Phase −50 100 Phase − Degrees −50 Gain −150 −200 1k 10k Frequency − Hz 100k Figure 3 Figure 3 shows an example of the gain and phase frequency response measurement of a power module. 6.
SLUU166A - December 2003 − Revised February 2004 A high-frequency pole, fPOLE configured with C4, should be added for noise filtering. C4 + 2 1 R 22 p f POLE (4) The total impedance at CS− must be mirrored at the non-inverting input, CS+, of the differential amplifier, as shown by R7, R16, and C1 in Figure 1. The CSA output voltage, VCSO, serves as the input to the internal unity gain LS bus driver.
SLUU166A - December 2003 − Revised February 2004 6.5 Error Amplifier Compensation The total load-share loop must be configured for a unity gain crossover frequency well before the crossover frequency of the module, fCOmodule, as measured in Figure 2 and shown in Figure 3. This is accomplished by placing a zero in the error amplifier compensation at least one decade before the module’s crossover frequency.
SLUU166A - December 2003 − Revised February 2004 7 List of Materials REFERENCE QTY DESCRIPTION MANUFACTURER PART NUMBER C1, C2, C3, C4, C6, C8 6 Capacitor, ceramic, X5R or better, CSA compensation, 0805 TBD TBD C10, C11, C12 3 Capacitor, ceramic, X5R or better, EA compensation, 1210 TBD TBD C5, C7, C9 3 Capacitor, ceramic, 0.47 µF, 25 V, X7R, ±10%, 0805 TDK Corporation C2012X7R1E474K Q1, Q2, Q3 3 MOSFET, N-channel, 60 V, 115 mA, 1.
SLUU166A - December 2003 − Revised February 2004 Figure 4. Lug Assembly Detail 8 Board Layout Figure 5.
SLUU166A - December 2003 − Revised February 2004 Figure 6. Top Layer Route Figure 7.
SLUU166A - December 2003 − Revised February 2004 9 Connection Diagram INPUT POWER SOURCE VOUT+ +VIN −VIN POWER MODULE 3 VOUT− S− S+ +VIN −VIN VOUT− POWER MODULE 2 VOUT+ VOUT− S− S+ A +VIN −VIN POWER MODULE 1 VOUT+ A VOUT− S− S+ VOUT+ A A LOAD Figure 8.
SLUU166A - December 2003 − Revised February 2004 Table 1. Connection Chart for Various Operating Conditions OPERATING CONDITIONS JUMPER POSITION COMMENTS JP1 Power module output voltage greater than 1V but less than 5V JP2 EXT. External minimum bias voltage of 4.575V for the Loads Share Controller required at the EXTERNAL BIAS terminal block INT.
SLUU166A - December 2003 − Revised February 2004 12 Appendix Example NOTE:The following calculations are given as an example. Actual circuit values will vary depending upon the specific modules used This design uses the UCC39002 to parallel three Texas Instrument PT4484 modules whose output voltages are nominally 5 V, the maximum output current of each module is 20 A, and a maximum output voltage adjustment range of 2% of the output voltage.
SLUU166A - December 2003 − Revised February 2004 Measuring the Module’s Unity Gain Crossover Frequency The unity gain crossover frequency of the module was measured at maximum load exactly as shown in Figure 8. The measured results are displayed in Figure 9. Measurement shows the module has a dc gain of approximately 65 dB, a zero at approximately 1100 Hz, one pole at 10 kHz, and a double pole at approximately 200 Hz, and the crossover frequency of the module, fCOMOD, was measured to be 25.
SLUU166A - December 2003 − Revised February 2004 The results of this gain-frequency measurement are approximated in the following equation and plotted in Figure 10: G MOD(f) + 65 10 20 1 ) s(f) ƪ1 ) s(f) ǒ2 1 p 10000 Hz ǒ2 1 p 1100 Hz Ǔ Ǔƫ ƪ1 ) s(f) ǒ2 1 p 200 Hz Ǔƫ 2 where: f + 100 Hz, 200 Hz, 50 kHz s(f) + j 2 p f logǒŤG MOD(f)ŤǓ G MODULE(f) + 20 Q MODULE(f) + argǒG MOD(f)Ǔ 180 p GAIN vs FREQUENCY 100 Gain − dB 50 0 −50 100 1000 10000 100000 Frequency − Hz Figure 11.
SLUU166A - December 2003 − Revised February 2004 PHASE vs FREQUENCY 0 Phase − Degrees −50 −100 −150 −200 100 1000 10000 100000 Frequency − Hz Figure 12. Phase-Frequency Mathematical Approximation of the PT4484 Module Choosing the Sense Resistor Because the current sense resistor is in series with the sense lines of the module, the voltage drop across the sense resistor, VRSENSE, must be subtracted from the maximum voltage adjustment range of the module.
SLUU166A - December 2003 − Revised February 2004 RSENSE is equal to the actual resistor value used based upon availability of standard values, two 0.002-Ω resistors are used in parallel: R SENSE + 1 mW PRSENSE is equal to the calculated power dissipation of the actual resistor used and VRsense is equal to its resultant voltage drop: P RSENSE + R SENSE I OUT(max) 2 P RSENSE + 0.4 W V RSENSE + I OUT(max) R SENSE V RSENSE + 0.02 V Confirm that VRSENSE is much less than ∆VADJ.
SLUU166A - December 2003 − Revised February 2004 fPOLE is equal to the added high frequency pole for noise roll off: f POLE + 50 kHz C CSA + 2 p 1 R CSA(1) f POLE C CSA + 31.831 pF CCSA is equal to the actual capacitor value selected for this pole: C CSA + 33 pF The resultant actual pole frequency: f POLE + 2 p 1 R CSA(1) C CSA f POLE + 48.229 kHz Note that these CSA compensation components must be on both input terminals of the differential amplifier.
SLUU166A - December 2003 − Revised February 2004 Determining RADJ IADJ(max) is equal to the maximum current that the internal adjust amplifier can sink: I ADJ(max) + 3 V 500 W I ADJ(max) + 6 mA A resistor, RADJ, is placed between the power module’s Sense+ terminal and the load.
SLUU166A - December 2003 − Revised February 2004 Error Amplifier Compensation System stability requires the load share circuit’s unity gain crossover frequency to be well before the unity gain crossover frequency of the power module, as measured in the first step of this design.
SLUU166A - December 2003 − Revised February 2004 R EAO + 10 W Actual resistor value used: R EAO + 10 W A bode plot of the load share open loop gain frequency response and comparing it to the original gain frequency response of the individual module is shown in Figure12: ǒ G ERRORAMP(f) + G M 1 s(f) C EAO ) R EAO Ǔ G LSOPENLOOP(f) + 20 logǒŤG CSA(f)ŤǓ ) 20 logǒŤA VŤǓ ) 20 logǒŤA ADJŤǓ ) 20 G TOTAL(f) + G LSOPENLOOP(f) ) G MODULE(f) GAIN vs FREQUENCY 80 60 GMODULE (f) 40 Gain − dB 20 0 GTOTA
SLUU166A - December 2003 − Revised February 2004 Figure 14.
SLUU166A - December 2003 − Revised February 2004 LOAD SHARE ERROR RESULT FOR THE PT4484 MODULES 10 8 Current Sharing Error − % 6 4 Module 3 2 0 Module 2 −2 Module 1 −4 −6 −8 −10 20 30 40 50 60 Total System Output Current − A Figure 15. Resultant Load Current Sharing Accuracy, as Measured Across Shunts from the Output of Each Module.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
