Datasheet

   
   
SLUS419C − AUGUST 1999 − REVISED NOVEMBER 2001
7
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pin assignments (continued)
SS2: (soft-start for PWM) SS2 is at ground for either enable low or OVP/ENBL below the UVLO2 threshold
conditions. When enabled, SS2 charges an external capacitor with a current source. This voltage is used as
the voltage error signal during start-up, enabling the PWM duty cycle to increase slowly. In the event of a disable
command or a UVLO2 dropout, SS2 quickly discharges to disable the PWM.
VAOUT: (voltage amplifier output) This is the output of the operational amplifier that regulates output voltage.
The voltage amplifier output is internally limited to approximately 5.5 V to prevent overshoot.
VCC: (positive supply voltage) Connect to a stable source of at least 20 mA between 12 V and 17 V for normal
operation. Bypass VCC directly to GND to absorb supply current spikes required to charge external MOSFET
gate capacitances. To prevent inadequate gate drive signals, the output devices are inhibited unless VCC
exceeds the upper under-voltage lockout threshold and remains above the lower threshold.
VERR: (voltage amp error signal for the second stage) The error signal is generated by an external amplifier
which drives this pin. This pin has an internal 4.5-V voltage clamp that limits GT2 to less than 50% duty cycle
to ensure transformer reset in the typical application.
VFF: (RMS feed forward signal) VFF signal is generated at this pin by mirroring one-half of I
AC
into a single pole
external filter. At low line, the VFF voltage should be 1.4 V.
VSENSE: (voltage amplifier inverting input) This is normally connected to a compensation network and to the
boost converter output through a divider network.
VREF: (voltage reference output) VREF is the output of an accurate 7.5-V voltage reference. This output is
capable of delivering 10 mA to peripheral circuitry and is internally short-circuit current limited. VREF is disabled
and remains at 0 V when VCC is below the UVLO threshold. Bypass VREF to GND with a 0.1-µF or larger
ceramic capacitor for best stability.