Datasheet
SLUS579 − OCTOBER, 2003
2
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DESCRIPTION (CONTINUED)
The UCC3819A is directly pin for pin compatible with the UCC3819. Only the output stage of UCC3819A has
been modified to allow use of a smaller external gate drive resistor values. For some power supply designs
where an adequately high enough gate drive resistor can not be used, the UCC3819A offers a more robust
output stage at the cost of increasing the internal gate resistances. The gate drive of the UCC3819A remains
strong at ±1.2 A of peak current capability.
Available in the 16-pin D, N, and PW packages.
PIN CONNECTION DIAGRAM
D, N, AND PW PACKAGES
(TOP VIEW)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
PKLMT
CAOUT
CAI
MOUT
IAC
VAOUT
VFF
DRVOUT
VCC
CT
VAI
RT
VSENSE
OVP/EN
VREF
AVAILABLE OPTIONS TABLE
T
A
= T
J
PACKAGE DEVICES
T
A
= T
J
SOIC (D) PACKAGE
(1)
PDIP (N) PACKAGE TSSOP (PW) PACKAGE
(1)
0°C to 70°C UCC3819AD UCC3819AN UCC3819APW
−40°C to 85°C UCC2819AD UCC2819AN UCC2819APW
NOTES: (1) The D and PW packages are available taped and reeled. Add R suffix to the device type (e.g. UCC3819ADR) to order quantities
of 2,500 devices per reel (D package) and 2,000 devices per reel (for PW package). Bulk quantities are 40 units (D package) and
90 units (PW package) per tube.
THERMAL RESISTANCE TABLE
PACKAGE θjc(°C/W) θja(°C/W)
SOIC−16 (D) 22 40 to 70
(1)
PDIP−16 (N) 12 25 to 50
(1)
TSSOP−16 (PW) 14
(2)
123 to 147
(2)
NOTES: (1) Specified θja (junction to ambient) is for devices mounted to 5-inch
2
FR4 PC board with one ounce copper
where noted. When resistance range is given, lower values are for 5 inch
2
aluminum PC board. Test PWB
was 0.062 inch thick and typically used 0.635-mm trace widths for power packages and 1.3-mm trace
widths for non-power packages with a 100-mil x 100-mil probe land area at the end of each trace.
(2) Modeled data. If value range given for θja, lower value is for 3x3 inch. 1 oz internal copper ground plane,
higher value is for 1x1-inch. ground plane. All model data assumes only one trace for each non-fused
lead.